Commits · f9a8c6a0e50540f68e6740a849a7caf5e4d46ca6 · Roger Ferrer / llvm-epi · GitLab

Apr 12, 2021
- [AMDGPU] Save VGPR of whole wave when spilling · f9a8c6a0
  Sebastian Neubauer authored Apr 12, 2021
  f9a8c6a0
- [AArch64] Adds memory operands for indexed loads. · a655f250
  Stelios Ioannou authored Apr 09, 2021
  a655f250
- [X86] Pass to transform tdpbsud&tdpbusd&tdpbuud intrinsics to scalar operation · 747111ea
  Bing1 Yu authored Mar 24, 2021
  747111ea
- [X86] Remove FeatureCLWB from FeaturesICLClient · 5cb47be4
  Freddy Ye authored Apr 12, 2021
  5cb47be4
- [PowerPC] Lower f128 SETCC/SELECT_CC as libcall if p9vector disabled · ece73458
  Qiu Chaofan authored Apr 12, 2021
  ece73458
- [RISCV][NFC] Remove unneeded explict XLenVT type on codegen patterns · a3bfddbb
  Jim Lin authored Apr 12, 2021
  a3bfddbb
- [RISCV] Update computeKnownBitsForTargetNode to treat READ_VLENB as being 16 byte aligned. · cb4c793e
  Craig Topper authored Apr 11, 2021
  cb4c793e
Apr 11, 2021
- [RISCV] Use SLLI/SRLI instead of SLLIW/SRLIW for (srl (and X, 0xffff), C) custom isel on RV64. · ff902080
  Craig Topper authored Apr 11, 2021
  ff902080
- [X86][AVX512] Fold not(kmov(x)) -> kmov(not(x)) and not(widen_subvector(x)) ->... · 231b8761
  Simon Pilgrim authored Apr 11, 2021
  231b8761
- [WebAssembly] Update v128.any_true · ea8dd3ee
  Thomas Lively authored Apr 11, 2021
  ea8dd3ee
- [X86] combineXor - Pull out repeated getOperand() calls. NFCI. · 13bdac57
  Simon Pilgrim authored Apr 11, 2021
  
  13bdac57
- [X86] Fold cmpeq/ne(and(X,Y),Y) --> cmpeq/ne(and(~X,Y),0) · 38c799bc
  Simon Pilgrim authored Apr 11, 2021
  38c799bc
- [RISCV] Drop earlyclobber constraint from vwadd(u).wx, vwsub(u).wx, vfwadd.wf and vfwsub.wf. · 3ae71226
  Craig Topper authored Apr 11, 2021
  3ae71226
- [RISCV] Teach targetShrinkDemandedConstant to preserve (and X, 0xffff) when zext.h is supported. · bc0e0527
  Craig Topper authored Apr 11, 2021
  bc0e0527
Apr 10, 2021
- [AMDGPU][CostModel] Refine cost model for control-flow instructions. · 8f4b7e94
  dfukalov authored Feb 16, 2021
  8f4b7e94
- Revert "[AMDGPU] Remove MachineDCE after SIFoldOperands" · 092f288d
  Mitch Phillips authored Apr 09, 2021
  092f288d
- Revert "[AMDGPU] SIFoldOperands: eagerly erase dead REG_SEQUENCEs" · 3d4730a7
  Mitch Phillips authored Apr 09, 2021
  3d4730a7
- [AArch64][GlobalISel] Swap compare operands when it may be profitable · 49c3565b
  Jessica Paquette authored Nov 09, 2020
  49c3565b
Apr 09, 2021
- Revert "[PowerPC] Add ROP Protection Instructions for PowerPC" · 1a2756b7
  Mitch Phillips authored Apr 09, 2021
  1a2756b7
- [AMDGPU] Remove MachineDCE after SIFoldOperands · 5a0117b2
  Jay Foad authored Apr 08, 2021
  5a0117b2
- [AMDGPU] SIFoldOperands: eagerly erase dead REG_SEQUENCEs · d19a42eb
  Jay Foad authored Apr 09, 2021
  d19a42eb
- Add correct types to the xxsplti32dx pattern. · 5bca7cda
  Stefan Pintilie authored Apr 09, 2021
  5bca7cda
- [WebAssembly] Add shuffles as an option for lowering BUILD_VECTOR · f30c429d
  Thomas Lively authored Apr 09, 2021
  f30c429d
- [AArch64][GlobalISel] Fix incorrect codegen for <16 x s8> G_ASHR. · 40e75caf
  Amara Emerson authored Apr 09, 2021
  40e75caf
- [PowerPC] Add ROP Protection Instructions for PowerPC · 16fe741c
  Stefan Pintilie authored Apr 09, 2021
  16fe741c
- [X86] Fold cmpeq/ne(or(X,Y),X) --> cmpeq/ne(and(~X,Y),0) on non-BMI targets (PR44136) · d8bc4de3
  Simon Pilgrim authored Apr 09, 2021
  d8bc4de3
- [X86][BMI] Fold cmpeq/ne(or(X,Y),X) --> cmpeq/ne(and(~X,Y),0) (PR44136) · 24503695
  Simon Pilgrim authored Apr 09, 2021
  24503695
- [AMDGPU] SIFoldOperands: eagerly delete dead copies · a4ced03d
  Jay Foad authored Apr 08, 2021
  a4ced03d
- [AMDGPU] Use SIInstrFlags for flat variants. NFC · cc7add52
  Sebastian Neubauer authored Mar 30, 2021
  cc7add52
- [NFC][AA] Prepare to convert AliasResult to class with PartialAlias offset. · d0660797
  dfukalov authored Mar 05, 2021
  d0660797
- [X86] combineHorizOpWithShuffle - peek through one use bitcasts when decoding shuffles. · 3ae0a405
  Simon Pilgrim authored Apr 08, 2021
  3ae0a405
- [AMDGPU] IsFlatScratch/Global -> FlatScratch/Global · 36138db1
  Sebastian Neubauer authored Apr 09, 2021
  36138db1
- [RISCV][NFC] Replace explicit type i64 with riscv customized SDTypeProfile. · 7eaa2810
  Jim Lin authored Apr 09, 2021
  7eaa2810
- [RISCV][NFC] Fix formatting · 6169f153
  Jim Lin authored Apr 09, 2021
  
  6169f153
- [RISCV][NFC] Add explicit type i64 to RV64 only patterns. · 49c79e3b
  Jim Lin authored Apr 09, 2021
  49c79e3b
- Use default ref capture to avoid unused capture warning on assert-used variable · 82940196
  David Blaikie authored Apr 08, 2021
  
  82940196
- [RISCV] Use multiclass inheritance where possible for the VPat* multiclasses... · 872931e5
  Craig Topper authored Apr 08, 2021
  872931e5
- [RISCV] Remove empty string after 'defm' at top level of vector .td files. NFC · ac347a8a
  Craig Topper authored Apr 08, 2021
  ac347a8a
Apr 08, 2021
- AMDGPU: Add gfx90c support to code object v2 for backwards compatibility · 4fae63c6
  Konstantin Zhuravlyov authored Apr 08, 2021
  4fae63c6
- [AMDGPU] Check for all meta instrs in GCNRegBankReassign · 627dab3d
  Stanislav Mekhanoshin authored Apr 08, 2021
  627dab3d