Commits · fcad2bbcfc1f0acaa91fe03b71ff069975f80c8e · Roger Ferrer / llvm-epi · GitLab

Aug 10, 2023
- [RISC-V] Add proposed mapping for Ztso · fcad2bbc
  Patrick O'Neill authored Aug 10, 2023
  fcad2bbc
- Revert "[DAG] Support store merging of vector constant stores" · 0696a531
  Philip Reames authored Aug 10, 2023
  0696a531
- [RISCV] Remove completed FIXME. NFC · b165a777
  Luke Lau authored Aug 10, 2023
  b165a777
- [RISCV] Fix zihintntl test · 8901eb28
  Jianjian GUAN authored Aug 10, 2023
  
  8901eb28
- [RISCV] Remove experimental for zihintntl · f8087884
  Jianjian GUAN authored May 26, 2023
  f8087884
- [RISCV] Enable alias analysis by default · 5f73d2b7
  Yunze Zhu authored Aug 08, 2023
  5f73d2b7
Aug 09, 2023
- [LegalizeTypes][RISCV] Correct FP_TO_{S,U}INT expansion when bf16 isn't a legal type · 89b8ebf3
  Alex Bradbury authored Aug 09, 2023
  89b8ebf3
Aug 08, 2023
- [LegalizeTypes][RISCV] Support libcalls for fpto{s,u}i of bfloat by extending to f32 first · f7dbc850
  Alex Bradbury authored Aug 08, 2023
  f7dbc850
- [RISCV] Lower vro{l,r} for fixed vectors · 5d510ea7
  Luke Lau authored Aug 07, 2023
  5d510ea7
- [RISCV] Lower unary zvbb ops for fixed vectors · 768740ef
  Luke Lau authored Aug 07, 2023
  768740ef
- [RISCV] Add fixed vector tests for ct[l,t]z_zero_undef · 44383ac7
  Luke Lau authored Aug 07, 2023
  44383ac7
- [RISCV] Use vmv.s.x for a constant build_vector when the entire size is less than 32 bits · f0a9aacd
  Philip Reames authored Aug 07, 2023
  f0a9aacd
- [RISCV][GlobalISel] Legalize G_ICMP and G_SELECT · c9fe1198
  Nitin John Raj authored Aug 07, 2023
  c9fe1198
- [RISCV][GlobalISel] Legalize add/sub for wide and non-pow2 types · cd61e8de
  Nitin John Raj authored Jul 28, 2023
  cd61e8de
- [RISCV][GlobalISel] Legalize logical instructions for nonpow 2 types · 3bcfd6e9
  Nitin John Raj authored Aug 07, 2023
  3bcfd6e9
- [RISCV][GlobalISel] Legalize bitshift instructions for narrow types · 649e1d1b
  Nitin John Raj authored Aug 07, 2023
  649e1d1b
Aug 07, 2023
- [RISCV] Add back handling of X > -1 to ISD::SETCC lowering. · 7cc61541
  Craig Topper authored Aug 07, 2023
  7cc61541
- [RISCV][GlobalISel] Legalize constants, undefined values, extension... · b8fef7a6
  Nitin John Raj authored Aug 07, 2023
  b8fef7a6
- [RISCV][GlobalISel] Fix tests for addition, subtraction and logical instructions · 1b74459d
  Nitin John Raj authored Aug 07, 2023
  1b74459d
- [RISCV] Use v(f)slide1down for build_vector with dominant values · 47fe3b3b
  Philip Reames authored Aug 07, 2023
  47fe3b3b
- [RISCVGatherScatterLowering] Support broadcast base pointer · 999ac10d
  Philip Reames authored Aug 07, 2023
  999ac10d
- [RISCV][test] Add non-zfbfmin RUN lines to bfloat-convert.ll · 380fd820
  Alex Bradbury authored Aug 07, 2023
  380fd820
- [RISCV] Add a blank line after end of RUN lines. NFC. · f2bdc29f
  Jim Lin authored Aug 04, 2023
  f2bdc29f
- [TargetLowering][RISCV] Improve codegen for saturating bf16 to int conversion · 1cffd264
  Alex Bradbury authored Aug 07, 2023
  1cffd264
- [RISCV] Implement straight-forward bf16<->int conversion cases · 7a1b2adc
  Alex Bradbury authored Aug 07, 2023
  7a1b2adc
Aug 04, 2023
- [RISCV] Add vector legalization for fmaximum/fminimum. · 81425019
  Craig Topper authored Aug 04, 2023
  81425019
Aug 03, 2023
- [RISCV] Add a test case that would have failed before D156974. NFC · 40f37082
  Craig Topper authored Aug 03, 2023
  40f37082
- [RISCV] Add bf16 to isFPImmLegal. · a8c502a5
  Craig Topper authored Aug 03, 2023
  a8c502a5
- [RISCV] emit .option directive for functions with target features which differ from module default · 05041b78
  Piyou Chen authored Aug 02, 2023
  05041b78
- [RISCV] Add tests that m extension enabled in extractelt-int-rv64.ll. NFC. · a2938ba7
  Jim Lin authored Aug 03, 2023
  a2938ba7
- [RISCV] Use max pushed register to get pushed register number. · f68c6879
  Yeting Kuo authored Aug 03, 2023
  f68c6879
- [RISCV] Expand test coverage of bf16 operations with Zfbfmin and fix gaps · 8a71f44e
  Alex Bradbury authored Aug 03, 2023
  8a71f44e
- [RISCV] Scalarize binop followed by extractelement to custom lowered instruction · 40cc106f
  Jim Lin authored Aug 03, 2023
  40cc106f
- [RISCV] Merge fp-imm.ll and zfh-imm.ll into float/double/half-imm.ll. NFC · c1c5da8f
  Craig Topper authored Aug 02, 2023
  c1c5da8f
- [RISCV] Teach lowerScalarInsert to handle scalar value is the first element of a fixed vector. · cd795993
  Yeting Kuo authored Aug 02, 2023
  cd795993
- [RISCV] Add VP patterns for vwsll.[vv,vx,vi] · 08343552
  Luke Lau authored Aug 02, 2023
  08343552
Aug 02, 2023
- [DAG] Support store merging of vector constant stores · 660b740e
  Philip Reames authored Aug 02, 2023
  660b740e
- [RISCV] Implement support for bf16 select when zfbfmin is enabled · 66760279
  Alex Bradbury authored Aug 02, 2023
  66760279
- [RISCV] Support vector crypto extension LLVM IR · 346c1f26
  4vtomat authored Jun 25, 2023
  346c1f26
- [RISCV] Add test case showing CSE regression from issue 64282 · fe4c99d1
  Philip Reames authored Aug 02, 2023
  
  fe4c99d1