Commits · fd3304ef8545081246f28cd37be98a05d6f24bdd · Roger Ferrer / llvm-epi · GitLab

Jun 10, 2022
- [AMDGPU] gfx11 EXECZ and VCCZ are no longer allowed to be used as · fd3304ef
  Joe Nash authored Jun 06, 2022
  fd3304ef
- [AMDGPU] Basic implementation of isExtractSubvectorCheap · 4b2d70fa
  Jay Foad authored Jun 07, 2022
  4b2d70fa
- [SimplifyCFG] Share code to compute switch density between... · 3800b157
  Hans Wennborg authored Jun 08, 2022
  3800b157
- [clang] Add support for __builtin_memset_inline · 38637ee4
  Guillaume Chatelet authored Jun 07, 2022
  38637ee4
- [RISCV] move `isFaultFirstLoad` into `RISCVInstrInfo` · e018e493
  Shao-Ce SUN authored Jun 10, 2022
  e018e493
- [X86] combineMulToPMADDWD - don't bitcast the source ops before splitting to... · 5acbb2dd
  Simon Pilgrim authored Jun 10, 2022
  5acbb2dd
- [NFC] Use proper getSliceAlign type in SROA · 12ccdd67
  Guillaume Chatelet authored Jun 10, 2022
  
  12ccdd67
- Revert "[InstCombine] add narrowing transform for low-masked binop with zext operand" · 6fedc6a2
  Sanjay Patel authored Jun 10, 2022
  6fedc6a2
- [AMDGPU][GFX9][GFX10] Support base+soffset+offset SMEM atomics. · 60d6fbb6
  Ivan Kosarev authored Jun 10, 2022
  60d6fbb6
- [InstCombine] Use +0.0 instead of -0.0 as the FP identity for some folds · 8daaea20
  David Sherwood authored May 31, 2022
  8daaea20
- [FuncSpec]Fix assertion failure when value is not added to solver · 8b360c69
  Bin Cheng authored Jun 10, 2022
  8b360c69
- [AMDGPU][MC][GFX1013] Enable image_msaa_load · f8aba999
  Dmitry Preobrazhensky authored Jun 10, 2022
  f8aba999
- [MVE] Fold fadd(select(..., +0.0)) into a predicated fadd · 007917b9
  David Sherwood authored Jun 08, 2022
  007917b9
- [LoopInfo] Add getOutermostLoop() (NFC) · d77f9448
  Nikita Popov authored Apr 10, 2021
  d77f9448
- [AggressiveInstcombine] Conditionally fold saturated fptosi to llvm.fptosi.sat · 4a5cb957
  David Green authored Jun 10, 2022
  4a5cb957
- [CGP] Also freeze ctlz/cttz operand when despeculating · c10921fa
  Nikita Popov authored May 30, 2022
  c10921fa
- [AMDGPU] New GFX11 intrinsic llvm.amdgcn.s.sendmsg.rtn · 6c372daa
  Jay Foad authored Jun 08, 2022
  6c372daa
- [AMDGPU] Update dlc usage for GFX11 · b0a38494
  Jay Foad authored Nov 04, 2021
  b0a38494
- [JITLink][EHFrameSupport] Remove CodeAlignmentFactor and DataAlignmentFactor validation. · 6d67f7a3
  Sunho Kim authored Jun 10, 2022
  6d67f7a3
- [RISCV] Lower VLEFF/VLSEGFF SDNodes to MachineInstrs with VL outputs. · f68cad90
  Yeting Kuo authored May 30, 2022
  f68cad90
- [ORC][ORC_RT] Handle ELF .init_array with non-default priority · 2be5abb7
  Peter S. Housel authored Jun 03, 2022
  2be5abb7
- [ORC][ORC_RT] Integrate ORC platforms with LLJIT and lli · 1aa71f86
  Peter S. Housel authored May 25, 2022
  1aa71f86
- [JITLink][ELF][AArch64] Implement Procedure Linkage Table. · 87c42683
  Sunho Kim authored Jun 10, 2022
  87c42683
- [ORC][AArch64] Add initial support for aarch64 in ELFNixPlatform. · e093e421
  Sunho Kim authored Jun 10, 2022
  e093e421
- [JITLink][ELF][AArch64] Implement R_AARCH64_JUMP26 · 175f22d6
  Sunho Kim authored Jun 10, 2022
  175f22d6
- [InstCombine] Optimize shl+lshr+and conversion pattern · de7a6ae1
  chenglin.bi authored Jun 10, 2022
  de7a6ae1
- [JITLink][AArch64] Fix overflow range of Page21 fixup edge. · 51a41f23
  Sunho Kim authored Jun 10, 2022
  51a41f23
- [RISCV] Simplify InstrInfo access in doPeepholeMaskedRVV [nfc] · 28be4b74
  Philip Reames authored Jun 09, 2022
  
  28be4b74
- [RISCV] Teach RISCVMergeBaseOffset about cases where we use SHXADD to add some immediates. · 8bbcb988
  Craig Topper authored Jun 09, 2022
  8bbcb988
- Plumb InstructionCost through unroll costing · 206f10d3
  Philip Reames authored Jun 09, 2022
  206f10d3
- Pipe potentially invalid InstructionCost through CodeMetrics · f85c5079
  Philip Reames authored Jun 09, 2022
  f85c5079
Jun 09, 2022
- [InstCombine] add narrowing transform for low-masked binop with zext operand · afa192cf
  Sanjay Patel authored Jun 09, 2022
  afa192cf
- [X86] Remove !VT.is128BitVector() check. NFCI. · 7ac33b8a
  Simon Pilgrim authored Jun 09, 2022
  7ac33b8a
- [AMDGPU] Update SIInsertHardClauses for GFX11 · ffe86e3b
  Jay Foad authored Jun 09, 2022
  ffe86e3b
- [X86][AVX2] LowerINSERT_VECTOR_ELT - support v4i64 insertion as BLENDI(X, SCALAR_TO_VECTOR(Y)) · 72a049d7
  Simon Pilgrim authored Jun 09, 2022
  
  72a049d7
- [Object][COFF] Fix section name parsing error when the name field is not null-padded · 064db243
  Pengxuan Zheng authored Jun 08, 2022
  064db243
- [AMDGPU] gfx11 VOPC instructions · be1082c6
  Joe Nash authored May 25, 2022
  be1082c6
- Reapply: Add an error message to the default SIGPIPE handler · b89bcefa
  Tim Northover authored Jun 09, 2022
  b89bcefa
- [AMDGPU] Use v_mad_u64_u32 for IMAD32 · 23db8e4b
  Stanislav Mekhanoshin authored Jun 06, 2022
  23db8e4b
- Revert "Add an error message to the default SIGPIPE handler" · 4badd4d4
  Tim Northover authored Jun 09, 2022
  4badd4d4