Commits · ff37b1105d6eb7b9a4e4515c2ced95e9837567aa · Roger Ferrer / llvm-epi · GitLab

Oct 22, 2021
- [LegalizeVectorOps][X86] Don't defer BITREVERSE expansion to LegalizeDAG. · ff37b110
  Craig Topper authored Oct 21, 2021
  ff37b110
Oct 21, 2021
- [TargetLowering][RISCV] Prevent scalarization of fixed vector bswap. · 458ed5fc
  Craig Topper authored Oct 21, 2021
  458ed5fc
- [AArch64][GlobalISel] Fold 64-bit cmps with 64-bit adds · 5dc339d9
  Jessica Paquette authored Oct 04, 2021
  5dc339d9
- BPF: emit BTF_KIND_DECL_TAG for typedef types · 0472e83f
  Yonghong Song authored Sep 20, 2021
  0472e83f
- [RISCV] Expand scalable vector CTTZ/CTLZ/CTPOP. · d55be79d
  Craig Topper authored Oct 21, 2021
  d55be79d
- [RISCV] Add a test showing incorrect VSETVLI insertion · 92673fad
  Fraser Cormack authored Oct 21, 2021
  92673fad
- [SystemZ][z/OS] Initial implementation for lowerCall on z/OS · aa3519f1
  Anirudh Prasad authored Oct 21, 2021
  aa3519f1
- [DAGCombiner] fold bit-hack form of usubsat · d2198771
  Sanjay Patel authored Oct 21, 2021
  d2198771
- [SVE] Fix selection failure when splitting extended masked loads · 0d153df6
  Kerry McLaughlin authored Oct 21, 2021
  0d153df6
- [ARM] Add new abs test. NFC · 9bfe7af1
  David Green authored Oct 21, 2021
  
  9bfe7af1
- [ARM] Use correct name of floating point ceil intrinsic in test. · b75f3dd8
  Craig Topper authored Oct 20, 2021
  b75f3dd8
Oct 20, 2021
- [x86] add special-case lowering for usubsat for AVX512 · 40163f1d
  Sanjay Patel authored Oct 20, 2021
  40163f1d
- [AArch64][GlobalISel] combine (and (or x, c1), c2) => (and x, c2) iff c1 & c2 == 0 · b046eb19
  Jon Roelofs authored Oct 14, 2021
  b046eb19
- [AMDGPU] MachineLICM cannot hoist VALU · c80d8a8c
  Stanislav Mekhanoshin authored Jul 23, 2021
  c80d8a8c
- [AMDGPU] Allow rematerialization of SOP with virtual registers · 61858356
  Stanislav Mekhanoshin authored Sep 24, 2021
  61858356
- [WebAssembly] Add prototype relaxed float min max instructions · e1fb1340
  Zhi An Ng authored Oct 20, 2021
  e1fb1340
- [RISCV][WebAssembly][TargetLowering] Allow expandCTLZ/expandCTTZ to rely on... · fe1f0de0
  Craig Topper authored Oct 19, 2021
  fe1f0de0
- [NewPM][test] Avoid using -enable-new-pm=1 since -passes implies new PM · a413663d
  Bjorn Pettersson authored Oct 20, 2021
  
  a413663d
- [SelectionDAG] Fix getVectorSubVecPointer for scalable subvectors. · be6c8dc7
  Sander de Smalen authored Oct 12, 2021
  be6c8dc7
- [AArch64] Emit .cfi_negate_ra_state for PAC-auth instructions. · f903c850
  Daniel Kiss authored Oct 20, 2021
  f903c850
- [WebAssembly] Implementation of table.get/set for reftypes in LLVM IR · 6d0c7bc1
  Paulo Matos authored Oct 07, 2021
  6d0c7bc1
- [WebAssembly] Add prototype relaxed swizzle instructions · 2542bfa4
  Zhi An Ng authored Oct 19, 2021
  2542bfa4
- BPF: set .BTF and .BTF.ext section alignment to 4 · cd40b5a7
  Yonghong Song authored Oct 19, 2021
  cd40b5a7
- [NVPTX] Add a late SROA pass which allows optimizing away more allocas. · b6b7fe60
  Artem Belevich authored Oct 08, 2021
  b6b7fe60
Oct 19, 2021
- [x86] add special-case lowering for usubsat for pre-SSE4 · 92a0389b
  Sanjay Patel authored Oct 19, 2021
  92a0389b
- [x86] add tests for psubus; NFC · e2faf721
  Sanjay Patel authored Oct 19, 2021
  
  e2faf721
- [AMDGPU] add test for usubsat; NFC · c1ca9e30
  Sanjay Patel authored Oct 19, 2021
  
  c1ca9e30
- [x86] add tests for psubus; NFC · 081bad1d
  Sanjay Patel authored Oct 19, 2021
  
  081bad1d
- [AArch64] Split out processor/tuning features · 5ea35791
  David Sherwood authored Sep 30, 2021
  5ea35791
- [RISCV] Reorder the vector register allocation order. · facff468
  Hsiangkai Wang authored Oct 07, 2021
  facff468
- [opt] Directly translate -O# to -passes='default<O#>' · 15fefcb9
  Arthur Eubanks authored Oct 18, 2021
  15fefcb9
- [HIP] [AlwaysInliner] Disable AlwaysInliner to eliminate undefined symbols · 0567f033
  Anshil Gandhi authored Oct 18, 2021
  0567f033
Oct 18, 2021
- [X86] combineMulToPMADDWD - replace ASHR(X,16) -> LSHR(X,16) · a8338449
  Simon Pilgrim authored Oct 18, 2021
  a8338449
- [X86] Regenerate testb-je-fusion.ll with common NOFUSION/FUSION prefixes · cdf9df65
  Simon Pilgrim authored Oct 18, 2021
  
  cdf9df65
- [x86] Implement a tagged-globals backend feature. · 431a5d84
  Matt Morehouse authored Oct 18, 2021
  431a5d84
- [AArch64][GlobalISel] combine and + [la]sr => ubfx · 1300677f
  Jon Roelofs authored Oct 14, 2021
  1300677f
- BPF: remove intrindics @llvm.stacksave() and @llvm.stackrestore() · 009f3a89
  Yonghong Song authored Oct 14, 2021
  009f3a89
- [Mips] Add glue between CopyFromReg, CopyToReg and RDHWR nodes for TLS · f5755c08
  Jessica Clarke authored Oct 18, 2021
  f5755c08
- [AArch64] Improve shuffle vector by using wider types · f5056c8c
  Andrew Wei authored Oct 18, 2021
  f5056c8c
- [AArch64][SVE][CodeGen] Add tests for RSHRN{T,B} instructions · c0782ba8
  Peter Waller authored Oct 18, 2021
  c0782ba8