Commits · ffa2dce59070636e0d83d2797fb80c4ca2d7ea2d · Roger Ferrer / llvm-epi · GitLab

Dec 02, 2020
- [PowerPC] Fix FLT_ROUNDS_ on little endian · ffa2dce5
  Qiu Chaofan authored Dec 02, 2020
  ffa2dce5
- [llvm-readelf/obj] - Refine the error message about the broken string table. · 01e49204
  Georgii Rymar authored Dec 01, 2020
  01e49204
- [Test] One CodeGen test showing missing opportunity on move elimination · 16bee4d3
  Max Kazantsev authored Dec 02, 2020
  
  16bee4d3
- [Test] One more IndVars test · 391a47e2
  Max Kazantsev authored Dec 02, 2020
  
  391a47e2
- [PowerPC] Promote the i1 to i64 for SINT_TO_FP/FP_TO_SINT · 47f784ac
  QingShan Zhang authored Dec 02, 2020
  47f784ac
- [WebAssembly] Support select and block for reference types · 60653e24
  Heejin Ahn authored Nov 30, 2020
  60653e24
- s/instantate/instantiate/ throughout. NFCI. · e181a6ae
  Arthur O'Dwyer authored Dec 01, 2020
  e181a6ae
- [VE] Add vcmp, vmax, and vmin intrinsic instructions · c1762bcf
  Kazushi (Jam) Marukawa authored Dec 01, 2020
  c1762bcf
- Fix typo in testcase runline that got there because I have very bad hands · b6b0a80e
  Jessica Paquette authored Dec 01, 2020
  b6b0a80e
- [AArch64][GlobalISel] Don't write to WZR in non-flag-setting G_BRCOND case · c82f002c
  Jessica Paquette authored Nov 02, 2020
  c82f002c
- [RISCVAsmParser] Allow a SymbolRef operand to be a complex expression · e27e3ba9
  Fangrui Song authored Dec 01, 2020
  e27e3ba9
- [AArch64][GlobalISel] Select Bcc when it's better than TB(N)Z · 6c3fa97d
  Jessica Paquette authored Nov 30, 2020
  6c3fa97d
- [ms] [llvm-ml] Support command-line defines · c64037b7
  Eric Astor authored Dec 01, 2020
  c64037b7
Dec 01, 2020
- [ms] [llvm-ml] Introduce command-line compatibility for ml.exe and ml64.exe · 8fee2ee9
  Eric Astor authored Nov 30, 2020
  8fee2ee9
- Revert "[FastISel] Flush local value map on ever instruction" and dependent patches · 615f63e1
  David Blaikie authored Dec 01, 2020
  615f63e1
- Revert "[LV] Epilogue Vectorization with Optimal Control Flow" · c94af03f
  Bardia Mahjour authored Dec 01, 2020
  c94af03f
- Let .llvm_bb_addr_map section use the same unique id as its associated .text section. · e0bf2349
  Rahman Lavaee authored Dec 01, 2020
  e0bf2349
- [BasicAA] Add test for suboptimal result with unknown sizes (NFC) · 54eab293
  Nikita Popov authored Dec 01, 2020
  
  54eab293
- [LV] Epilogue Vectorization with Optimal Control Flow · 9c5504ad
  Bardia Mahjour authored Dec 01, 2020
  9c5504ad
- [MemCpyOpt] Port to MemorySSA · 624af932
  Nikita Popov authored Oct 02, 2020
  624af932
- [X86] Support modifier @PLTOFF for R_X86_64_PLTOFF64 · f0659c06
  Fangrui Song authored Dec 01, 2020
  f0659c06
- [InstSimplify] Add tests that fold instructions with poison operands (NFC) · 864dda5f
  Juneyoung Lee authored Dec 02, 2020
  
  864dda5f
- [MergeICmps] Fix missing split. · 735e6c88
  Clement Courbet authored Dec 01, 2020
  735e6c88
- [x86] adjust cost model values for minnum/maxnum with fast-math-flags · 136f98e5
  Sanjay Patel authored Dec 01, 2020
  136f98e5
- [ARM] Mark select and selectcc of MVE vector operations as expand. · eedf0ed6
  David Green authored Dec 01, 2020
  eedf0ed6
- [InstCombine] canonicalize sign-bit-shift of difference to ext(icmp) · 9f60b8b3
  Sanjay Patel authored Dec 01, 2020
  9f60b8b3
- [DAG] Move vselect(icmp_ult, 0, sub(x,y)) -> usubsat(x,y) to DAGCombine (PR40111) · 1b209ff9
  Simon Pilgrim authored Dec 01, 2020
  1b209ff9
- [ConstraintElimination] Decompose GEP %ptr, ZEXT(SHL()). · 7a4f1d59
  Florian Hahn authored Nov 30, 2020
  7a4f1d59
- [VE] Add vmul and vdiv intrinsic instructions · 10b164d2
  Kazushi (Jam) Marukawa authored Dec 01, 2020
  10b164d2
- [X86] Add PR48223 usubsat test case · 00f4269c
  Simon Pilgrim authored Dec 01, 2020
  
  00f4269c
- [InstCombine] Optimize away the unnecessary multi-use sign-extend · fd679107
  Bhramar Vatsa authored Dec 01, 2020
  fd679107
- [InstCombine] Improve vector undef handling for sext(ashr(shl(trunc()))) fold, 2 · 94ead019
  Roman Lebedev authored Dec 01, 2020
  94ead019
- [InstCombine] add tests for sign-bit-shift-of-sub; NFC · b2cdd776
  Sanjay Patel authored Dec 01, 2020
  
  b2cdd776
- Remove rm -f cortex-a57-misched-mla.s; hopefully the bots have all cycled past it now · 2ca4785a
  Hans Wennborg authored Dec 01, 2020
  
  2ca4785a
- Revert "[InstCombine] Improve vector undef handling for sext(ashr(shl(trunc()))) fold" · 52533b52
  Roman Lebedev authored Dec 01, 2020
  52533b52
- [NFC][InstCombine] sext.ll: @test9: avoid only differently-cased names for values and block names · 55c06a30
  Roman Lebedev authored Dec 01, 2020
  
  55c06a30
- [InstCombine] Improve vector undef handling for sext(ashr(shl(trunc()))) fold · aa1aa135
  Roman Lebedev authored Dec 01, 2020
  aa1aa135
- [NFC][InstCombine] Improve vector undef test coverage for sext(ashr(shl(trunc()))) fold · 075faa8d
  Roman Lebedev authored Dec 01, 2020
  
  075faa8d
- [InstCombine] Evaluate new shift amount for sext(ashr(shl(trunc()))) fold in wide type (PR48343) · 8e29e20e
  Roman Lebedev authored Dec 01, 2020
  8e29e20e
- [NFC][InstCombine] Add PR48343 miscompiled testcase · 799626b1
  Roman Lebedev authored Dec 01, 2020
  
  799626b1