- Aug 28, 2017
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Craig Topper authored
[X86] Use getUnpackl helper to create an ISD::VECTOR_SHUFFLE instead of using X86ISD::UNPCKL in reduceVMULWidth. This runs fairly early, we should use target independent nodes if possible. llvm-svn: 311873
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Craig Topper authored
Without this the madd.ll and sad.ll test cases both throw assertions if you run them with SSE2 disabled. llvm-svn: 311872
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Lang Hames authored
handleExpected is similar to handleErrors, but takes an Expected<T> as its first input value and a fallback functor as its second, followed by an arbitary list of error handlers (equivalent to the handler list of handleErrors). If the first input value is a success value then it is returned from handleErrors unmodified. Otherwise the contained error(s) are passed to handleErrors, along with the handlers. If handleErrors returns success (indicating that all errors have been handled) then handleExpected runs the fallback functor and returns its result. If handleErrors returns a failure value then the failure value is returned and the fallback functor is never run. This simplifies the process of re-trying operations that return Expected values. Without this utility such retry logic is cumbersome as the internal Error must be explicitly extracted from the Expected value, inspected to see if its handleable and then consumed: enum FooStrategy { Aggressive, Conservative }; Expected<Foo> tryFoo(FooStrategy S); Expected<Foo> Result; (void)!!Result; // "Check" Result so that it can be safely overwritten. if (auto ValOrErr = tryFoo(Aggressive)) Result = std::move(ValOrErr); else { auto Err = ValOrErr.takeError(); if (Err.isA<HandleableError>()) { consumeError(std::move(Err)); Result = tryFoo(Conservative); } else return std::move(Err); } with handleExpected, this can be re-written as: auto Result = handleExpected( tryFoo(Aggressive), []() { return tryFoo(Conservative); }, [](HandleableError&) { /* discard to handle */ }); llvm-svn: 311870
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Dehao Chen authored
struct string { ~string(); }; void f2(); void f1(int) { f2(); } void run(int c) { string body; while (true) { if (c) f1(c); else f1(c); } } Will recommit once the issue is fixed. llvm-svn: 311864
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- Aug 27, 2017
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Petar Jovanovic authored
This patch enables generation of NMADD and NMSUB instructions when fneg node is present. These instructions are currently only generated if fsub node is present. Patch by Stanislav Ocovaj. Differential Revision: https://reviews.llvm.org/D34507 llvm-svn: 311862
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Javed Absar authored
Move condition code support functions to Utils and remove code duplication. Reviewed by: @fhahn, @asb Differential Revision: https://reviews.llvm.org/D37179 llvm-svn: 311860
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Craig Topper authored
[AVX512] Add more patterns for using masked moves for subvector extracts of the lowest subvector. This time with bitcasts between the vselect and the extract. llvm-svn: 311856
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Sanjay Patel authored
As noted in the FIXME, this could be improved more, but this is the smallest fix that helps: https://bugs.llvm.org/show_bug.cgi?id=34111 llvm-svn: 311853
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Sanjay Patel authored
llvm-svn: 311852
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Javed Absar authored
Simplify getDRegFromQReg function Reviewed by: @fhahn, @asb Differential Revision: https://reviews.llvm.org/D37118 llvm-svn: 311850
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Ayal Zaks authored
Original commit r311077 of D32871 was reverted in r311304 due to failures reported in PR34248. This recommit fixes PR34248 by restricting the packing of predicated scalars into vectors only when vectorizing, avoiding doing so when unrolling w/o vectorizing. Added a test derived from the reproducer of PR34248. llvm-svn: 311849
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Jatin Bhateja authored
llvm-svn: 311847
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Craig Topper authored
[X86] Add a target-specific DAG combine to combine extract_subvector from all zero/one build_vectors. llvm-svn: 311841
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Craig Topper authored
llvm-svn: 311840
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Davide Italiano authored
llvm-svn: 311838
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Craig Topper authored
[AVX512] Add patterns to match masked extract_subvector with bitcasts between the vselect and the extract_subvector. Remove the late DAG combine. We used to do a late DAG combine to move the bitcasts out of the way, but I'm starting to think that it's better to canonicalize extract_subvector's type to match the type of its input. I've seen some cases where we've formed two different extract_subvector from the same node where one had a bitcast and the other didn't. Add some more test cases to ensure we've also got most of the zero masking covered too. llvm-svn: 311837
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- Aug 26, 2017
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Don Hinton authored
Summary: Remove redundant explicit template instantiation. This was reported by Andrew Kelley building release_50 with gcc7.2.0 on MacOS: duplicate symbol llvm::DominatorTreeBase. Reviewers: kuhar, andrewrk, davide, hans Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D37185 llvm-svn: 311835
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Jatin Bhateja authored
Differential Revision: https://reviews.llvm.org/D37183 llvm-svn: 311834
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Jatin Bhateja authored
Summary: If all the operands of a BUILD_VECTOR extract elements from same vector then split the vector efficiently based on the maximum vector access index. This will also fix PR 33784 Reviewers: zvi, delena, RKSimon, thakis Reviewed By: RKSimon Subscribers: chandlerc, eladcohen, llvm-commits Differential Revision: https://reviews.llvm.org/D35788 llvm-svn: 311833
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Jatin Bhateja authored
Summary: This reverts commit rL311247. Differential Revision: https://reviews.llvm.org/D36927 llvm-svn: 311832
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Daniel Berlin authored
NewGVN: Fix PR33204 - We need to add memory users when we bypass memorydefs for loads, not just when we do it for stores. llvm-svn: 311829
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Craig Topper authored
We were suppressing most uses of INC/DEC, but this one seems to have been missed. llvm-svn: 311828
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Petr Hosek authored
This reverts commit r311826 because it's failing on llvm-i686-linux-RA. llvm-svn: 311827
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Petr Hosek authored
This change adds support for SHT_SYMTAB sections. Patch by Jake Ehrlich Differential Revision: https://reviews.llvm.org/D34167 llvm-svn: 311826
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Petr Hosek authored
The current file layout algorithm in llvm-objcopy is simple but difficult to reason about. It also makes it very complicated to support nested segments and to support segments that have offsets that come before a point after the program headers. To support these cases and simplify one of the most critical parts llvm-objcopy I rewrote the layout algorithm. Laying out segments first solves most of the issues encountered by the previous algorithm. Patch by Jake Ehrlich Differential Revision: https://reviews.llvm.org/D36494 llvm-svn: 311825
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Hiroshi Yamauchi authored
Summary: Add options -print-bfi/-print-bpi that dump block frequency and branch probability info like -view-block-freq-propagation-dags and -view-machine-block-freq-propagation-dags do but in text. This is useful when the graph is very large and complex (the dot command crashes, lines/edges too close to tell apart, hard to navigate without textual search) or simply when text is preferred. Reviewers: davidxl Reviewed By: davidxl Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D37165 llvm-svn: 311822
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Craig Topper authored
[AVX512] Add patterns to use masked moves to implement masked extract_subvector of the lowest subvector. This only supports 32 and 64 bit element sizes for now. But we could probably do 16 and 8-bit elements with BWI. llvm-svn: 311821
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Craig Topper authored
This includes tests for extracting 128-bits from a 256-bit vector and zero masking. llvm-svn: 311820
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Craig Topper authored
We can probably add patterns to fix some of them. But the ones that use 'and' as their root node emit a X86ISD::CMP node in front of the 'and' and then pattern matching that to 'test' instruction. We can't use a tablegen pattern to fix that because we can't remap the cmp result to the flag output of a TBM instruction. llvm-svn: 311819
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Chandler Carruth authored
to instructions. These can't be reasonably matched in tablegen due to the handling of flags, so we have to do this in C++ code. We only did it for `inc` and `dec` historically, this starts fleshing that out to more interesting instructions. Notably, this handles transfering operands to `add` and `sub`. Currently this forces them into a register. The next patch will add support for keeping immediate operands as immediates. Then I'll extend this beyond just `add` and `sub`. I'm not super thrilled by the repeated switches in the code but everything else I tried was really ugly or problematic. Many thanks to Craig Topper for the suggestions about where to even begin here and how to make this stuff work. Differential Revision: https://reviews.llvm.org/D37130 llvm-svn: 311806
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Davide Italiano authored
Fixes PR34325. llvm-svn: 311805
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Davide Italiano authored
Prior to this change (and after r311371), we computed it unconditionally, causin gsevere compile time regressions (in some cases, 5 to 10x). llvm-svn: 311804
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Matt Morehouse authored
This reverts r311801 due to a bot failure. llvm-svn: 311803
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- Aug 25, 2017
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Matt Morehouse authored
Summary: - Don't sanitize __sancov_lowest_stack. - Don't instrument leaf functions. - Add CoverageStackDepth to Fuzzer and FuzzerNoLink. Reviewers: vitalybuka, kcc Reviewed By: kcc Subscribers: cfe-commits, llvm-commits, hiraditya Differential Revision: https://reviews.llvm.org/D37156 llvm-svn: 311801
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Sanjay Patel authored
I don't know enough to add a custom scrubber for AArch64, so I just re-used ARM. llvm-svn: 311795
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Kostya Serebryany authored
llvm-svn: 311794
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Sanjay Patel authored
llvm-svn: 311793
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Haicheng Wu authored
Change the early exit condition from Cost > Threshold to Cost >= Threshold because the inline condition is Cost < Threshold. Differential Revision: https://reviews.llvm.org/D37087 llvm-svn: 311791
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Craig Topper authored
[InstCombine] Don't fall back to only calling computeKnownBits if the upper bit of Add/Sub is demanded. Just create an all 1s demanded mask and continue recursing like normal. The recursive calls should be able to handle an all 1s mask and do the right thing. The only time we should care about knowing whether the upper bit was demanded is when we need to know if we should clear the NSW/NUW flags. Now that we have a consistent path through the code for all cases, use KnownBits::computeForAddSub to compute the known bits at the end since we already have the LHS and RHS. My larger goal here is to move the code that turns add into xor if only 1 bit is demanded and no bits below it are non-zero from InstCombiner::OptAndOp to here. This will allow it to be more general instead of just looking for 'add' and 'and' with constant RHS. Differential Revision: https://reviews.llvm.org/D36486 llvm-svn: 311789
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Craig Topper authored
[InstCombine] Add tests to show missed opportunities to combine bit tests hidden by a sign compare and a truncate. NFC llvm-svn: 311784
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