We use the branch instruction as the location at which a PHI-node write takes
place, instead of the PHI-node itself. This allows us to identify the
basic-block in a region statement which is on the incoming edge of the PHI-node
and for which the write access was originally introduced. As a result we can,
during code generation, avoid generating PHI-node write accesses for basic
blocks that do not preceed the PHI node without having to look at the IR
again.

This change fixes a bug which was introduced in r243420, when we started to
explicitly model PHI-node reads and writes, but dropped some additional checks
that where still necessary during code generation to not emit PHI-node writes
for basic-blocks that are not on incoming edges of the original PHI node.
Compared to the code before r243420 the new code does not need to inspect the IR
any more and we also do not generate multiple redundant writes.

llvm-svn: 243852

This patch fixes bug 23800 ( https://llvm.org/bugs/show_bug.cgi?id=23800#c2 ). There existed a case where the index operand from extractelement was directly used to create a shufflevector mask. Since the index can be of any integral type but the mask must only contain 32 bit integers a 64 bit index operand led to an assertion error later on.

Committed on behalf of mpflanzer (Moritz Pflanzer)

Differential Revision: http://reviews.llvm.org/D10838

llvm-svn: 243851

llvm-svn: 243850

The schedule map we derive from a schedule tree map may map statements into
schedule spaces of different dimensionality. This change adds zero padding
to ensure just a single schedule space is used and the translation from
a union_map to an isl_multi_union_pw_aff does not fail.

llvm-svn: 243849

add 128 & 256 width intrinsic versions of reduce/range and cvt i64 to FP and vice versa

Differential Revision: http://reviews.llvm.org/D11598

llvm-svn: 243848

Summary: As per title

Reviewers: chandlerc, bogner, majnemer, axw

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D11141

llvm-svn: 243847

working with (the Communication m_bytes ivar) contained a single packet.
Instead, it may contain multitudes.  Find the boundaries of the first packet
in the buffer and replace that with the decompressed version leaving the
rest of the buffer unmodified.
<rdar://problem/21841377> 

llvm-svn: 243846

llvm-svn: 243845

Mark Type::getPointerTo as const. Unfortunately, this requires a const_cast inside, but at least it makes all methods on Type const. NFC

llvm-svn: 243844

Merge the const and non-const Type::getScalarType to a const version that returns a non-const pointer. Since we don't put const on Types all places were already calling the non-const version.

llvm-svn: 243843

This was already done in most places a while ago. This just fixes the ones that crept in over time.

llvm-svn: 243842

llvm-svn: 243841

Until I figure out what's the right way of updating this file.

llvm-svn: 243840

Summary:
Fixes PR24303. With Bruno's WIP (D11197) on PeepholeOptimizer, across-class
register copying (e.g. i32 to f32) becomes possible. Enhance
NVPTXInstrInfo::copyPhysReg to handle these cases.

Reviewers: jholewinski

Subscribers: eliben, jholewinski, llvm-commits, bruno

Differential Revision: http://reviews.llvm.org/D11622

llvm-svn: 243839

llvm-svn: 243838

llvm-svn: 243837

llvm-svn: 243836

llvm-svn: 243835

llvm-svn: 243833

llvm-svn: 243832

The XformToShuffleWithZero method currently checks AND masks at the per-lane level for all-one and all-zero constants and attempts to convert them to legal shuffle clear masks.

This patch generalises XformToShuffleWithZero, splitting and checking the sub-lanes of the constants down to the byte level to see if any legal shuffle clear masks are possible. This allows a lot of masks (often from legalization or truncation) to be folded into existing shuffle patterns and removes a lot of constant mask loading.

There are a few examples of poor shuffle lowering that are exposed by this patch that will be cleaned up in future patches (e.g. merging shuffles that are separated by bitcasts, x86 legalized v8i8 zero extension uses PMOVZX+AND+AND instead of AND+PMOVZX, etc.)

Differential Revision: http://reviews.llvm.org/D11518

llvm-svn: 243831

SCEVExpander, which we are using during code generation, only allows
instructions as insert locations, but breaks in case BasicBlock->end() iterators
are passed to it due to it trying to obtain the basic block in which code should
be generated by calling Instruction->getParent(), which is not defined for
->end() iterators.

This change adds an assert to Polly that ensures we only pass valid instructions
to SCEVExpander and it fixes one case, where we used IRBuilder->SetInsertBlock()
to set an ->end() insert location which was later passed to SCEVExpander.

In general, Polly is always trying to build up the CFG first, before we actually
insert instructions into the CFG sceleton. As a result, each basic block should
already have at least one branch instruction before we start adding code. Hence,
always requiring the IRBuilder insert location to be set to a real instruction
should always be possible.

Thanks Utpal Bora <cs14mtech11017@iith.ac.in> for his help with test case
reduction.

llvm-svn: 243830

llvm-svn: 243829

Extended vector types are mangled just like normal vector types.

llvm-svn: 243828

llvm-svn: 243827

No functional change intended, just a drive-by cleanup.

llvm-svn: 243826

Remove some unnecessary explicit special members in Hexagon that, once
removed, allow the other implicit special members to be used without
depending on deprecated features.

llvm-svn: 243825

llvm-svn: 243824

llvm-svn: 243823

Summary: Also test 64-bit integers, except shifts for now which are broken because isel dislikes the 32-bit truncate that precedes them.

Reviewers: sunfish

Subscribers: llvm-commits, jfb

Differential Revision: http://reviews.llvm.org/D11699

llvm-svn: 243822

llvm-svn: 243821

Various targets use std::swap on specific MCAsmOperands (ARM and
possibly Hexagon as well). It might be helpful to mark those subclasses
as final, to ensure that the availability of move/copy operations can't
lead to slicing. (same sort of requirements as the non-vitual dtor -
protected or a final class)

llvm-svn: 243820

This patch should not change the test results, but it is useful if clang's
default C++ language is ever changed from gnu++98.

Patch by: Charles Li

http://lists.cs.uiuc.edu/pipermail/cfe-commits/Week-of-Mon-20150727/134667.html

llvm-svn: 243819

llvm-svn: 243818

llvm-svn: 243817

llvm-svn: 243816

ld.bfd fails to find dependencies of asan runtime library w/o an
extra -rpath-link pointing to usr/lib under the sysroot. Gold does
not have this problem.

llvm-svn: 243802

llvm-svn: 243801

llvm-svn: 243800

This commit fixes a bug in the class 'SIInstrInfo' where the implicit register
machine operands were added to a machine instruction in an incorrect order -
the implicit uses were added before the implicit defs.

I found this bug while working on moving the implicit register operand
verification code from the MIR parser to the machine verifier.

This commit also makes the method 'addImplicitDefUseOperands' in the machine
instruction class public so that it can be reused in the 'SIInstrInfo' class.

Reviewers: Matt Arsenault

Differential Revision: http://reviews.llvm.org/D11689

llvm-svn: 243799