Enabling merging of extern globals appears to be generally either beneficial or
harmless. On some benchmarks suites (on Cortex-M4F, Cortex-A9, and Cortex-A57)
it gives improvements in the 1-5% range, but in the rest the overall effect is
zero.

Differential Revision: http://reviews.llvm.org/D10966

llvm-svn: 243874

Adjust the GlobalMergeOnExternal option so that the default behaviour is to
do whatever the Target thinks is best. Explicitly enabled or disabling the
option will override this default.

Differential Revision: http://reviews.llvm.org/D10965

llvm-svn: 243873

The test/DebugInfo/dwarfdump-macho-universal.test test added in r243862 uses
an input from another test's directory (test/tools/dsymutil/Inputs/fat-test.o)
which breaks our test setup.

Copying the required test input to the test's Input directory to fix the issue.

llvm-svn: 243872

commit review.

llvm-svn: 243871

Compiler crashed when vector elements / global register vars were used in inline assembler with "m" restriction. This patch fixes this.

Differential Revision: http://reviews.llvm.org/D10476

llvm-svn: 243870

In http://reviews.llvm.org/rL215382, IT forming was made more conservative under
the belief that a flag-setting instruction was unpredictable inside an IT block on ARMv6M.

But actually, ARMv6M doesn't even support IT blocks so that's impossible. In the ARMARM for
v7M, v7AR and v8AR it states that the semantics of such an instruction changes inside an
IT block - it doesn't set the flags. So actually it is fine to use one inside an IT block
as long as the flags register is dead afterwards.

This gives significant performance improvements in a variety of MPEG based workloads.

Differential revision: http://reviews.llvm.org/D11680

llvm-svn: 243869

When RUN: lines are split into multiple lines, each one must be prefixed with
RUN:.

llvm-svn: 243868

Differential Revision: http://reviews.llvm.org/D11642

llvm-svn: 243867

This is a minor optimization to only check for unresolved operands
inside `mapDistinctNode()` if the operands have actually changed.  This
shouldn't really cause any change in behaviour.  I didn't actually see a
slowdown in a profile, I was just poking around nearby and saw the
opportunity.

llvm-svn: 243866

llvm-svn: 243865

llvm-svn: 243864

llvm-svn: 243863

llvm-svn: 243862

llvm-svn: 243861

Summary: This currently sets the shift amount RHS to the same type as the LHS, and assumes that the LHS is a simple type. This isn't currently the case e.g. with weird integers sizes, but will eventually be true and will assert if not. That's what you get for having an experimental backend: break it and you get to keep both pieces. Most backends either set the RHS to MVT::i32 or MVT::i64, but WebAssembly is a virtual ISA and tries to have regular-looking binary operations where both operands are the same type (even if a 64-bit RHS shifter is slightly silly, hey it's free!).

Subscribers: llvm-commits, sunfish, jfb

Differential Revision: http://reviews.llvm.org/D11715

llvm-svn: 243860

llvm-svn: 243859

Change `DIELoc` and `DIEBlock` to stop inheriting from `DIE`, instead
inheriting from `DIEValueList` to share the value storage API.  This
awkward bit of code-sharing was also fairly confusing: neither `DIELoc`
nor `DIEBlock` represents a `DIE`, so why would they inherit from it?

Aside from the API cleanup, this should improve debug info memory usage
in the backend, since it shaves five pointers off of every `DIELoc` and
`DIEBlock`.  I haven't bothered to measure the savings, though.

llvm-svn: 243858

Use `DIEValueList` as a pointer to either `DIEBlock` or `DIELoc` instead
of `DIE`, since soon they won't inherit from the latter.

llvm-svn: 243857

Split out a helper `printValues()` for printing `DIEBlock` and `DIELoc`,
instead of relying on `DIE::print()`.  The shared code was actually
fairly small there.  No functionality change intended.

llvm-svn: 243856

Take `DIEValueList` instead of `DIE` so that `DIEBlock` and `DIELoc` can
stop inheriting from `DIE` in a future commit.

llvm-svn: 243855

Rewrite `DIEValueList` as a subclass of `DIE`, renaming its API to match
`DIE`'s.  This is preparation for changing `DIEBlock` and `DIELoc` to
stop inheriting from `DIE` and inherit directly from `DIEValueList`.

I thought about leaving this as a has-a relationship (and changing
`DIELoc` and `DIEBlock` to also have-a `DIEValueList`), but that seemed
to require a fair bit more boilerplate and I think it needed more
changes to the `DwarfUnit` API than this will.

No functionality change intended here.

llvm-svn: 243854

llvm-svn: 243853

We use the branch instruction as the location at which a PHI-node write takes
place, instead of the PHI-node itself. This allows us to identify the
basic-block in a region statement which is on the incoming edge of the PHI-node
and for which the write access was originally introduced. As a result we can,
during code generation, avoid generating PHI-node write accesses for basic
blocks that do not preceed the PHI node without having to look at the IR
again.

This change fixes a bug which was introduced in r243420, when we started to
explicitly model PHI-node reads and writes, but dropped some additional checks
that where still necessary during code generation to not emit PHI-node writes
for basic-blocks that are not on incoming edges of the original PHI node.
Compared to the code before r243420 the new code does not need to inspect the IR
any more and we also do not generate multiple redundant writes.

llvm-svn: 243852

This patch fixes bug 23800 ( https://llvm.org/bugs/show_bug.cgi?id=23800#c2 ). There existed a case where the index operand from extractelement was directly used to create a shufflevector mask. Since the index can be of any integral type but the mask must only contain 32 bit integers a 64 bit index operand led to an assertion error later on.

Committed on behalf of mpflanzer (Moritz Pflanzer)

Differential Revision: http://reviews.llvm.org/D10838

llvm-svn: 243851

llvm-svn: 243850

The schedule map we derive from a schedule tree map may map statements into
schedule spaces of different dimensionality. This change adds zero padding
to ensure just a single schedule space is used and the translation from
a union_map to an isl_multi_union_pw_aff does not fail.

llvm-svn: 243849

add 128 & 256 width intrinsic versions of reduce/range and cvt i64 to FP and vice versa

Differential Revision: http://reviews.llvm.org/D11598

llvm-svn: 243848

Summary: As per title

Reviewers: chandlerc, bogner, majnemer, axw

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D11141

llvm-svn: 243847

working with (the Communication m_bytes ivar) contained a single packet.
Instead, it may contain multitudes.  Find the boundaries of the first packet
in the buffer and replace that with the decompressed version leaving the
rest of the buffer unmodified.
<rdar://problem/21841377> 

llvm-svn: 243846

llvm-svn: 243845

Mark Type::getPointerTo as const. Unfortunately, this requires a const_cast inside, but at least it makes all methods on Type const. NFC

llvm-svn: 243844

Merge the const and non-const Type::getScalarType to a const version that returns a non-const pointer. Since we don't put const on Types all places were already calling the non-const version.

llvm-svn: 243843

This was already done in most places a while ago. This just fixes the ones that crept in over time.

llvm-svn: 243842

llvm-svn: 243841

Until I figure out what's the right way of updating this file.

llvm-svn: 243840

Summary:
Fixes PR24303. With Bruno's WIP (D11197) on PeepholeOptimizer, across-class
register copying (e.g. i32 to f32) becomes possible. Enhance
NVPTXInstrInfo::copyPhysReg to handle these cases.

Reviewers: jholewinski

Subscribers: eliben, jholewinski, llvm-commits, bruno

Differential Revision: http://reviews.llvm.org/D11622

llvm-svn: 243839

llvm-svn: 243838

llvm-svn: 243837

llvm-svn: 243836

llvm-svn: 243835