Commits · 22053c0f46d803884d90c664aa0df1a9149a0e2c · Roger Ferrer / llvm-epi-0.8

Nov 02, 2009
- Put BlockAddresses into ARM constant pools. · 1c66e8a6
  Bob Wilson authored Nov 02, 2009
```
llvm-svn: 85824
```
  1c66e8a6
- Fix schedule model for BFC. · 5ac6f244
  David Goodwin authored Nov 02, 2009
```
llvm-svn: 85809
```
  5ac6f244
Oct 30, 2009
- Add ARM codegen for indirect branches. · 1cf0b030
  Bob Wilson authored Oct 30, 2009
```
clang/test/CodeGen/indirect-goto.c runs! (unoptimized)

llvm-svn: 85577
```
  1cf0b030
Oct 28, 2009
- Add a Thumb BRIND pattern. Change the ARM BRIND assembly to separate the · 73789b84
  Bob Wilson authored Oct 28, 2009
```
opcode and operand with a tab.  Check for these instructions in the usual
places.

llvm-svn: 85411
```
  73789b84
- Add an indirect branch pattern for ARM. Testcase will be coming soon. · e4b80c9b
  Bob Wilson authored Oct 28, 2009
```
llvm-svn: 85355
```
  e4b80c9b
Oct 27, 2009
- Similar to r85280, do not clear the "S" bit for RSBri and RSBrs. · cde65ec5
  Johnny Chen authored Oct 27, 2009
```
llvm-svn: 85299
```
  cde65ec5
- Set condition code bits of BL and BLr9 to 0b1110 (ALways) to distinguish between · 4f36affe
  Johnny Chen authored Oct 27, 2009
```
BL_pred and BLr9_pred.

llvm-svn: 85297
```
  4f36affe
- Do not clear the "S" bit for RSCri and RSCrs. They inherit from the "sI" · b5044ce5
  Bob Wilson authored Oct 27, 2009
```
instruction format that already takes care of setting this.

llvm-svn: 85280
```
  b5044ce5
- Explicitly specify 0b00, i.e, zero rotation, as the rotate filed (Inst{11-10}) · df5dcdaa
  Johnny Chen authored Oct 27, 2009
```
for the r/rr fragment of the multiclass AI_unary_rrot/AI_bin_rrot.

llvm-svn: 85271
```
  df5dcdaa
- Change ARM asm strings to separate opcode from operands with a tab instead of a space. · 13edef55
  Evan Cheng authored Oct 26, 2009
```
llvm-svn: 85178
```
  13edef55
Oct 26, 2009
- Try to get ahead of Johnny Chen and pro-actively add some more ARM encoding · a33fa471
  Bob Wilson authored Oct 26, 2009
```
bits.  Johnny, please review -- I do not have a good track record of getting
these right.

llvm-svn: 85173
```
  a33fa471
- Add more ARM instruction encodings for 's' bit set and "rs" register encoding · a6aba77e
  Bob Wilson authored Oct 26, 2009
```
bits.  Patch by Johnny Chen.

llvm-svn: 85167
```
  a6aba77e
Oct 21, 2009
- Improve handling of immediates by splitting 32-bit immediates into two 16-bit · a93ca3c6
  Jim Grosbach authored Oct 21, 2009
```
immediate operands when they will fit into the using instruction.

llvm-svn: 84778
```
  a93ca3c6
- Match more patterns to movt. · 786b15fe
  Evan Cheng authored Oct 21, 2009
```
llvm-svn: 84751
```
  786b15fe
Oct 20, 2009
- implement printSORegOperand, add lowering for the nasty and despicable MOVi2pieces :) · 2f69ed8f
  Chris Lattner authored Oct 20, 2009
```
llvm-svn: 84573
```
  2f69ed8f
Oct 14, 2009
- Set instruction encoding bits 4 and 7 for ARM register-register and · 1a791eed
  Bob Wilson authored Oct 14, 2009
```
register-shifted-register instructions.  Patch by Johnny Chen.

llvm-svn: 84124
```
  1a791eed
Oct 13, 2009
- Add ARMv6T2 SBFX/UBFX instructions. Approved by Anton Korobeynikov. · 423e42b3
  Sandeep Patel authored Oct 13, 2009
```
llvm-svn: 84009
```
  423e42b3
- Add some ARM instruction encoding bits. · 453a06e3
  Bob Wilson authored Oct 13, 2009
```
Patch by Johnny Chen.

llvm-svn: 83983
```
  453a06e3
- Fix a tab. Thanks to Johnny Chen for pointing it out. · 0bc673de
  Bob Wilson authored Oct 13, 2009
```
llvm-svn: 83973
```
  0bc673de
Oct 10, 2009
- Mark the LDR instruction with isReMaterializable, as it is rematerializable · 4a72f7ab
  Dan Gohman authored Oct 09, 2009
```
when loading from an invariant memory location.

llvm-svn: 83688
```
  4a72f7ab
Oct 06, 2009
- Fix a comment typo. · dc7d1ce5
  Bob Wilson authored Oct 06, 2009
```
Patch by Johnny Chen.

llvm-svn: 83407
```
  dc7d1ce5
Oct 01, 2009
- Add hasExtraSrcRegAllocReq and hasExtraDefRegAllocReq flags to ld / st multiple, · 1b2b64f6
  Evan Cheng authored Oct 01, 2009
```
ld / st pairs, etc.

llvm-svn: 83197
```
  1b2b64f6
- Change ld/st multiples to explicitly model the writeback to base register.... · 3bbc6c3a
  Evan Cheng authored Oct 01, 2009
```
Change ld/st multiples to explicitly model the writeback to base register. This fixes most of the -ldstopti-before-sched2 regressions.

llvm-svn: 83191
```
  3bbc6c3a
Sep 30, 2009
- Add "isBarrier = 1" to return instructions. · bcad0c84
  Jim Grosbach authored Sep 30, 2009
```
Patch by Sylvere Teissier.

llvm-svn: 83135
```
  bcad0c84
Sep 28, 2009
- Make ARM and Thumb2 32-bit immediate materialization into a single 32-bit pseudo · 83e0d481
  Evan Cheng authored Sep 28, 2009
```
instruction. This makes it re-materializable.

Thumb2 will split it back out into two instructions so IT pass will generate the
right mask. Also, this expose opportunies to optimize the movw to a 16-bit move.

llvm-svn: 82982
```
  83e0d481
- Fix thinko in my recent movt commit: it's not safe to remat movt, since it has input reg argument. · c30d816d
  Anton Korobeynikov authored Sep 28, 2009
```
Disable rematting of it for now.

llvm-svn: 82975
```
  c30d816d
- Use movt/movw pair to materialize 32 bit constants on ARMv6T2+. · 7c2b1e71
  Anton Korobeynikov authored Sep 27, 2009
```
This should be better than single load from constpool.

llvm-svn: 82948
```
  7c2b1e71
Sep 09, 2009
- Fix arm jit encoding bug introduced by 75048. Some instructions', e.g. MOVi, bit 25 should be set. · 9fa8345b
  Evan Cheng authored Sep 09, 2009
```
llvm-svn: 81310
```
  9fa8345b
Sep 04, 2009
- Calls clobber FPSCR. · d93c668f
  David Goodwin authored Sep 03, 2009
```
llvm-svn: 80956
```
  d93c668f
Sep 01, 2009
- RRX reads CPSR. · 5f582b72
  David Goodwin authored Sep 01, 2009
```
llvm-svn: 80699
```
  5f582b72
Aug 28, 2009
- Print a nl before pic labels so they start at a new line. This makes assembly more readable. · 4047b53a
  Evan Cheng authored Aug 28, 2009
```
llvm-svn: 80350
```
  4047b53a
Aug 27, 2009
- STRD and LDRD require ARMv5TE, not just ARMv5T. · 209baa5c
  Misha Brukman authored Aug 27, 2009
```
See http://llvm.org/PR4687 for more info and links.

llvm-svn: 80244
```
  209baa5c
Aug 21, 2009

Rename ARM "lane_cst" operands to "nohash_imm" since they are used for · ceffeb6a

Bob Wilson authored Aug 21, 2009

several things other than Neon vector lane numbers.  For inline assembly
operands with a "c" print code, check that they really are immediates.

llvm-svn: 79676

ceffeb6a

Aug 19, 2009
- Update Cortex-A8 instruction itineraries for integer instructions. · a7c2dfbc
  David Goodwin authored Aug 19, 2009
```
llvm-svn: 79436
```
  a7c2dfbc
Aug 13, 2009
- Add missing defs of R2 and D1. · eba70d85
  Jim Grosbach authored Aug 13, 2009
```
llvm-svn: 78918
```
  eba70d85
- Finalize itineraries for cortex-a8 integer multiply · a9c2aad9
  David Goodwin authored Aug 13, 2009
```
llvm-svn: 78908
```
  a9c2aad9
- Remove unnecessary newline · 695e1c60
  Jim Grosbach authored Aug 13, 2009
```
llvm-svn: 78905
```
  695e1c60
- Correct comment wording · c96e88f8
  Jim Grosbach authored Aug 13, 2009
```
llvm-svn: 78904
```
  c96e88f8
Aug 12, 2009

Enhance the InstrStage object to enable the specification of an Itinerary with... · b369ee4c

David Goodwin authored Aug 12, 2009

Enhance the InstrStage object to enable the specification of an Itinerary with overlapping stages. The default is to maintain the current behavior that the "next" stage immediately follows the previous one.

llvm-svn: 78827

b369ee4c