Not turning them on yet.

llvm-svn: 106295

does for {flags}. If we create virtual registers of the CCR class, RegAllocFast
may try to spill them, and we can't do that.

llvm-svn: 106289

SDNode *, since it doesn't care about the ResNo value.

llvm-svn: 106282

llvm-svn: 106280

llvm-svn: 106279

llvm-svn: 106278

llvm-svn: 106273

to track a node over CSE events. This fixes PR7368.

llvm-svn: 106266

llvm-svn: 106264

which is faster, simpler, and less surprising.

llvm-svn: 106263

be done incrementally and intermixed with the adding of more
AVX instructions. This is a first step in that direction

llvm-svn: 106251

addresses a longstanding deficiency noted in many FIXMEs scattered
across all the targets.

This effectively moves the problem up one level, replacing eleven
FIXMEs in the targets with eight FIXMEs in CodeGen, plus one path
through FastISel where we actually supply a DebugLoc, fixing Radar
7421831.

llvm-svn: 106243

ISD::MEMBARRIER. v7 and v7 ARM mode continue to use the custom lowering.

llvm-svn: 106204

previously would result in 'cannot yet select' errors.

llvm-svn: 106199

TLVP:

movl _a@TLVP, %eax

Daniel: Please review if you get a chance.
llvm-svn: 106194

llvm-svn: 106173

This is before LiveVariables anyway, where these kill flags are recalculated.

llvm-svn: 106157

now, so there's no need to disable them.

llvm-svn: 106155

llvm-svn: 106102

Make post-ra scheduling, anti-dep breaking, and register scavenger (conservatively) aware of predicated instructions. This enables ARM to move if-conversion before post-ra scheduler.

llvm-svn: 106091

will conflict with another live range. The place which creates this scenerio is
the code in X86 that lowers a select instruction by splitting the MBBs. This
eliminates the need to check from the bottom up in an MBB for live pregs.

llvm-svn: 106066

a relative address.

llvm-svn: 106064

llvm-svn: 106058

call must not be callee-saved; following x86, add a new
regclass to represent this.  Also fixes a couple of bugs.
Still disabled by default; Thumb doesn't work yet.

llvm-svn: 106053

flag argument to addReg is not the same format as flags attached
to MachineOperand, although both have the same info.  I don't
think this actually mattered; the bootstrap failure did not
reproduce on the next run anyway.

llvm-svn: 106049

Nelson Elhage!

llvm-svn: 106031

llvm-svn: 106030

llvm-svn: 105994

llvm-svn: 105990

llvm-svn: 105988

containing the target address, an input, into an output.  I don't
think this actually broke anything on x86 (it does on ARM), but
it's wrong.

llvm-svn: 105986

the combined load/store instruction. rdar://7797940

llvm-svn: 105982

immediate" operands.  These functions have so far only been used for VMOV
but they also apply to other NEON instructions with modified immediate
operands.  No functional changes.

llvm-svn: 105969

symbols as declarations in the X86 backend.  This would manifest
on darwin x86-32 as errors like this with -fvisibility=hidden:

symbol '__ZNSbIcED1Ev' can not be undefined in a subtraction expression

This fixes PR7353.

llvm-svn: 105954

llvm-svn: 105943

more clear what exactly is missing.

llvm-svn: 105934

llvm-svn: 105900

llvm-svn: 105878

llvm-svn: 105876

llvm-svn: 105873