llvm-svn: 62763

Eliminate a couple of fields from TargetRegisterClass: SubRegClasses and SuperRegClasses. These are not necessary. Also eliminate getSubRegisterRegClass and getSuperRegisterRegClass. These are slow and their results can change if register file names change. Just use TargetLowering::getRegClassFor() to get the right TargetRegisterClass instead.

llvm-svn: 62762

llvm-svn: 62761

llvm-svn: 62760

analyses could be run without the caches properly sorted.  This
can fix all sorts of weirdness.  Many thanks to Bill for coming
up with the 'issorted' verification idea.

llvm-svn: 62757

to be supported in the JIT.

llvm-svn: 62730

ASCII IR; loading and storing these can change the
bits of NaNs on some hosts.  Remove or add warnings
at a few other places using host floating point;
this is a bad thing to do in general.

llvm-svn: 62712

llvm-svn: 62710

llvm-svn: 62699

PR3364

llvm-svn: 62697

compatibility with cygwin.  Patch by Jay Foad!

llvm-svn: 62695

special cases after producing the new reduced-width load, because the
new load already has the needed adjustments built into it. This fixes
several bugs due to the special cases, including PR3317.

llvm-svn: 62692

we want to clear %ah to zero before a division, just use a
zero-extending mov to %al. This fixes PR3366.

llvm-svn: 62691

llvm-svn: 62688

llvm-svn: 62681

prototypes, in operand type legalization.  No
functionality change.

llvm-svn: 62680

I accidentally removed this check in an earlier commit, which cause breakage in the pre alloc splitter.

llvm-svn: 62678

Also a few signed comparison fixes.

llvm-svn: 62665

- Ensure that (operation) legalization emits proper FDIV libcall when needed.
- Fix various bugs encountered during llvm-spu-gcc build, along with various
  cleanups.
- Start supporting double precision comparisons for remaining libgcc2 build.
  Discovered interesting DAGCombiner feature, which is currently solved via
  custom lowering (64-bit constants are not legal on CellSPU, but DAGCombiner
  insists on inserting one anyway.)
- Update README.

llvm-svn: 62664

Allow targets to legalize operations (with illegal operands) that produces multiple values. For example, a load with an illegal operand (a load produces two values, a value and chain).

llvm-svn: 62663

unsigned test(unsigned a) {
  return ~a;
}
llvm used to generate:
movl    $4294967295, %eax
xorl    4(%esp), %eax

Now it generates:
movl      4(%esp), %eax
notl      %eax

It's 3 bytes shorter.

llvm-svn: 62661

Besides APFloat, this involved removing code
from two places that thought they knew the
result of frem(0., x) but were wrong.

llvm-svn: 62645

llvm-svn: 62639

llvm-svn: 62638

llvm-svn: 62625

Fix PR3243: a LiveVariables bug. When HandlePhysRegKill is checking whether the last reference is also the last def (i.e. dead def), it should also check if last reference is the current machine instruction being processed. This can happen when it is processing a physical register use and setting the current machine instruction as sub-register's last ref.

llvm-svn: 62617

llvm-svn: 62616

causing the limited precision stuff to produce the wrong result for values in
the range [0, 1).

llvm-svn: 62615

llvm-svn: 62610

llvm-svn: 62602

llvm-svn: 62600

llvm-svn: 62596

llvm-svn: 62594

fully implemented yet and not used.  This is
mainly to clarify that APFloat::mod implements
C fmod, not remainder.

llvm-svn: 62593

Patrick Boettcher!

llvm-svn: 62592

llvm-svn: 62590

llvm-svn: 62589

llvm-svn: 62573

llvm-svn: 62571

llvm-svn: 62561