llvm-svn: 85355

llvm-svn: 85299

BL_pred and BLr9_pred.

llvm-svn: 85297

instruction format that already takes care of setting this.

llvm-svn: 85280

for the r/rr fragment of the multiclass AI_unary_rrot/AI_bin_rrot.

llvm-svn: 85271

llvm-svn: 85178

bits.  Johnny, please review -- I do not have a good track record of getting
these right.

llvm-svn: 85173

bits.  Patch by Johnny Chen.

llvm-svn: 85167

immediate operands when they will fit into the using instruction.

llvm-svn: 84778

llvm-svn: 84751

llvm-svn: 84573

register-shifted-register instructions.  Patch by Johnny Chen.

llvm-svn: 84124

llvm-svn: 84009

Patch by Johnny Chen.

llvm-svn: 83983

llvm-svn: 83973

when loading from an invariant memory location.

llvm-svn: 83688

Patch by Johnny Chen.

llvm-svn: 83407

ld / st pairs, etc.

llvm-svn: 83197

Change ld/st multiples to explicitly model the writeback to base register. This fixes most of the -ldstopti-before-sched2 regressions.

llvm-svn: 83191

Patch by Sylvere Teissier.

llvm-svn: 83135

instruction. This makes it re-materializable.

Thumb2 will split it back out into two instructions so IT pass will generate the
right mask. Also, this expose opportunies to optimize the movw to a 16-bit move.

llvm-svn: 82982

Disable rematting of it for now.

llvm-svn: 82975

This should be better than single load from constpool.

llvm-svn: 82948

llvm-svn: 81310

llvm-svn: 80956

llvm-svn: 80699

llvm-svn: 80350

See http://llvm.org/PR4687 for more info and links.

llvm-svn: 80244

several things other than Neon vector lane numbers.  For inline assembly
operands with a "c" print code, check that they really are immediates.

llvm-svn: 79676

llvm-svn: 79436

llvm-svn: 78918

llvm-svn: 78908

llvm-svn: 78905

llvm-svn: 78904

Enhance the InstrStage object to enable the specification of an Itinerary with overlapping stages. The default is to maintain the current behavior that the "next" stage immediately follows the previous one.

llvm-svn: 78827

llvm-svn: 78806

the latter is capable of representing either a primitive or an extended type.

llvm-svn: 78713

and short. Well, it's kinda short. Definitely nasty and brutish.

The front-end generates the register/unregister calls into the SjLj runtime,
call-site indices and landing pad dispatch. The back end fills in the LSDA
with the call-site information provided by the front end. Catch blocks are
not yet implemented.

Built on Darwin and verified no llvm-core "make check" regressions.

llvm-svn: 78625

llvm-svn: 78610

'no_hash' modifier. Hopefully this will make Daniel happy :)

llvm-svn: 78514