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  1. Jan 11, 2010
    • Evan Cheng's avatar
      Select an OR with immediate as an ADD if the input bits are known zero. This... · 64d9f405
      Evan Cheng authored
      Select an OR with immediate as an ADD if the input bits are known zero. This allow the instruction to be 3address-fied if needed.
      
      llvm-svn: 93152
      64d9f405
    • David Greene's avatar
      · 206351a1
      David Greene authored
      Implement a feature (-vector-unaligned-mem) to allow targets to
      ignore alignment requirements for SIMD memory operands.  This
      is useful on architectures like the AMD 10h that do not trap on
      unaligned references if a status bit is twiddled at startup time.
      
      llvm-svn: 93151
      206351a1
  2. Jan 09, 2010
  3. Jan 08, 2010
  4. Jan 07, 2010
  5. Jan 06, 2010
    • Evan Cheng's avatar
      Teach dag combine to fold the following transformation more aggressively: · 166a4e6c
      Evan Cheng authored
      (OP (trunc x), (trunc y)) -> (trunc (OP x, y))
      
      Unfortunately this simple change causes dag combine to infinite looping. The problem is the shrink demanded ops optimization tend to canonicalize expressions in the opposite manner. That is badness. This patch disable those optimizations in dag combine but instead it is done as a late pass in sdisel.
      
      This also exposes some deficiencies in dag combine and x86 setcc / brcond lowering. Teach them to look pass ISD::TRUNCATE in various places.
      
      llvm-svn: 92849
      166a4e6c
  6. Jan 05, 2010
  7. Jan 04, 2010
  8. Dec 29, 2009
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  10. Dec 26, 2009
  11. Dec 23, 2009
  12. Dec 22, 2009
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