llvm-svn: 118999

llvm-svn: 118998

- Get the opcode once.
- Add a ParserMatchClass to reglist.

llvm-svn: 118997

future to separate out the ia, ib, da, db variants of the load/store multiple
instructions.

llvm-svn: 118995

llvm-svn: 118985

llvm-svn: 118968

llvm-svn: 118965

instructions.

llvm-svn: 118963

flag for the LDRT/STRT family instructions as a side effect.

llvm-svn: 118955

llvm-svn: 118945

Eliminate ARM::MOVi2pieces. Just use MOVi32imm and expand it to either movi+orr or movw+movt depending on the subtarget.

llvm-svn: 118938

llvm-svn: 118935

llvm-svn: 118926

to splitting the load/store pre/post indexed instructions into [r, r] and
[r, imm] forms.

llvm-svn: 118925

llvm-svn: 118907

llvm-svn: 118829

instructions.

llvm-svn: 118801

llvm-svn: 118794

llvm-svn: 118767

llvm-svn: 118761

llvm-svn: 118757

encoding bits.

llvm-svn: 118738

llvm-svn: 118736

llvm-svn: 118732

llvm-svn: 118730

llvm-svn: 118600

llvm-svn: 118513

llvm-svn: 118462

llvm-svn: 118457

an initial implementation and may change once reglists are fully fleshed out.

llvm-svn: 118390

Fix @llvm.prefetch isel. Selecting between pld / pldw using the first immediate rw. There is currently no intrinsic that matches to pli.

llvm-svn: 118237

Fix preload instruction isel. Only v7 supports pli, and only v7 with mp extension supports pldw. Add subtarget attribute to denote mp extension support and legalize illegal ones to nothing.

llvm-svn: 118160

llvm-svn: 118152

    vldr.64 d1, [r0, #-32]

The problem was with how the addressing mode 5 encodes the offsets. This change
makes sure that the way offsets are handled in addressing mode 5 is consistent
throughout the MC code. It involves re-refactoring the "getAddrModeImmOpValue"
method into an "Imm12" and "addressing mode 5" version. But not to worry! The
majority of the duplicated code has been unified.

llvm-svn: 118144

parts. Represent the operation mode as an optional operand instead.
rdar://8614429

llvm-svn: 118137

ins/outs list that isn't specified by their asmstring.  Previously
the asmmatcher would just force a 0 register into it, which clearly
isn't right.  Mark a bunch of ARM instructions that use this as 
isCodeGenOnly.  Some of them are clearly pseudo instructions (like
t2TBB) others use a weird hasExtraSrcRegAllocReq thing that will
either need to be removed or the asmmatcher will need to be taught
about it (someday).

llvm-svn: 118119

with immediates up to 16-bits in size. The same logic is applied to other LDR
encodings, e.g. VLDR, but which use a different immediate bit width (8-bits in
VLDR's case). Removing the "12" allows it to be more generic.

llvm-svn: 118094

llvm-svn: 118093

llvm-svn: 118029

llvm-svn: 117997