We still don't handle

* default values
* :req
* :vararg
* \()

llvm-svn: 132656

VK_GOTOFF reloc. This matches as' behavior, but it is not clear why the linker
might need this, so I added a FIXME.

I could test this by duplicating test/MC/ELF/got.s, but it doesn't look
worthwhile.

llvm-svn: 132655

TypeLegalizer: Add support for passing of vector-promoted types in registers (copyFromParts/copyToParts).

llvm-svn: 132649

(only happens when using the -promote-elements option).

The correct legalization order is to first try to promote element. Next, we try
to widen vectors.

llvm-svn: 132648

rules. Also refactor "read string until quote" into its own function. No
functionality change!

llvm-svn: 132645

llvm-svn: 132643

then we don't want to set the destination in the indirect branch to the
destination. This is because the indirect branch needs its destinations to have
had their block addresses taken. This isn't so of the new critical edge that's
split during this process. If it turns out that the destination block has only
one predecessor, and that being a BB with an indirect branch, then it won't be
marked as 'used' and may be removed.
PR10072

llvm-svn: 132638

is disabled.

llvm-svn: 132632

redundant with partially-aliasing loads.

When computing what portion of a clobbering load value is needed,
it doesn't consider phi-translation which may have occurred
between the clobbing load and the redundant load.

llvm-svn: 132631

llvm-svn: 132625

llvm-svn: 132620

llvm-svn: 132616

BranchProbabilityInfo provides an interface for IR passes to query the
likelihood that control follows a CFG edge. This patch provides an
initial implementation of static branch predication that will populate
BranchProbabilityInfo for branches with no external profile
information using very simple heuristics. It currently isn't hooked up
to any external profile data, so static prediction does all the work.

llvm-svn: 132613

it exposed are fixed.

llvm-svn: 132611

queries in the case of a DAG, where a query reaches a node
visited earlier, but it's not on a cycle. This avoids
MayAlias results in cases where BasicAA is expected to
return MustAlias or PartialAlias in order to protect TBAA.

llvm-svn: 132609

rdar://problem/5993888

llvm-svn: 132606

Materializing the stack pointer update before a call requires a scratch
register that may not be available.

llvm-svn: 132601

constraint lengths.

Part of rdar://9037836 and rdar://9119939

llvm-svn: 132598

Part of rdar://9037836 and rdar://9119939

llvm-svn: 132590

of reserved registers.

Use RegisterClassInfo in RABasic as well. This slightly changes som
allocation orders because RegisterClassInfo puts CSR aliases last.

llvm-svn: 132581

Previously, these aliases would be ordered alphabetically. (BH, BL)

Print out the computed allocation orders.

llvm-svn: 132580

of conservatively choosing MayAlias.

llvm-svn: 132579

llvm-svn: 132578

addressing mode problem mentioned in r132559.

Backend part of rdar://9037836 and part of rdar://9119939

llvm-svn: 132561

llvm-svn: 132559

llvm-svn: 132558

A typedef's context is not the same as type's context. It is the context of typedef decl itself. Use extra parameter to communicate this to DIBuilder.

llvm-svn: 132556

llvm-svn: 132555

- Check for MTCTR8 in addition to MTCTR when looking up a hazard.

- When lowering an indirect call use CTR8 when targeting 64bit.

- Introduce BCTR8 that uses CTR8 and use it on 64bit when expanding ISD::BRIND.

The last change fixes PR8487. With those changes, we are able to compile a
running "ls" and "sh" on FreeBSD/PowerPC64.

llvm-svn: 132552

integers with high 32 bits being zero.

llvm-svn: 132538

which edge to split by pred/succ pair, which means that we can end up splitting
the wrong edge (by case value) in the switch statement entirely. Fixes PR10031!

llvm-svn: 132535

llvm-svn: 132533

Add ARM fast-isel support for materializing the address of a global in cases where the global uses an indirect symbol.

rdar://9431157

llvm-svn: 132522

Added asserts whenever attempting to use a potentially
uninitialized pass. This helps people trying to develop a new pass and
people trying to understand the bug reports filed by the former people.

llvm-svn: 132520

llvm-svn: 132519

When compiling a program with lots of small functions like
483.xalancbmk, this makes RAFast 11% faster.

Add some comments to clarify the difference between unallocatable and
reserved registers. It's quite subtle.

The fast register allocator depends on EFLAGS' not being allocatable on
x86. That way it can completely avoid tracking liveness, and it won't
mind when there are multiple uses of a single def.

llvm-svn: 132514

Part of rdar://9119939

llvm-svn: 132510

allocation orders.

llvm-svn: 132509

Some register classes are only used for instruction operand constraints.
They should never be used for virtual registers. Previously, those
register classes were given an empty allocation order, but now you can
say 'let isAllocatable=0' in the register class definition.

TableGen calculates if a register is part of any allocatable register
class, and makes that information available in TargetRegisterDesc::inAllocatableClass.

The goal here is to eliminate use cases for overriding allocation_order_*
methods.

llvm-svn: 132508

llvm-svn: 132505