- Apr 11, 2018
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Petr Hosek authored
This was removed in D39932 but turned out this is actually needed because runtimes such as compiler-rt and libc++ rely on common options processing for setting certain flags such as -ffunction-sections and -fdata-sections. Differential Revision: https://reviews.llvm.org/D45507 llvm-svn: 329778
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Craig Topper authored
[X86] Remove 128/256-bit masked pmaddubsw and pmaddwd intrinsics. Replace 512-bit masked intrinsic with unmasked intrinsic and a select. The 128/256-bit versions were no longer used by clang. It uses the legacy SSE/AVX2 version and a select. The 512-bit was changed to the same for consistency. llvm-svn: 329774
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Craig Topper authored
[X86] In X86FlagsCopyLowering, when rewriting a memory setcc we need to emit an explicit MOV8mr instruction. Previously the code only knew how to handle setcc to a register. This should fix a crash in the chromium build. llvm-svn: 329771
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Craig Topper authored
llvm-svn: 329769
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Sriraman Tallam authored
With -fno-plt, for example, calls to printf when getting converted to puts still use the PLT. This patch checks for the metadata "RtLibUseGOT" and annotates the declaration with the right attributes. Differential Revision: https://reviews.llvm.org/D45180 llvm-svn: 329768
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Rui Ueyama authored
llvm-svn: 329767
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Sriraman Tallam authored
With -fno-plt, global value references can use GOTPCREL and RIP must be used. Differential Revision: https://reviews.llvm.org/D45460 llvm-svn: 329765
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Marek Olsak authored
Author: Samuel Pitoiset ds_read_b128 and ds_write_b128 have been recently enabled under the amdgpu-ds128 option because the performance benefit is unclear. Though, using 128-bit loads/stores for the local address space appears to introduce regressions in tessellation shaders. Not sure what is broken, but as ds_read_b128/ds_write_b128 are not enabled by default, just introduce a global option and enable 128-bit only if requested (until it's fixed/used correctly). v2: - fix regressions in merge-stores.ll and multiple_tails.ll Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=105464 llvm-svn: 329764
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Galina Kistanova authored
llvm-svn: 329763
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- Apr 10, 2018
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Geoff Berry authored
Summary: When inserting MOVs to avoid Falkor HWPF collisions, the non-base register operand of load instructions (e.g. a register offset) was not being considered live, so it could potentially have been used as a scratch register, clobbering the actual offset value. Reviewers: mcrosier Subscribers: rengolin, javed.absar, kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D45502 llvm-svn: 329761
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Sanjay Patel authored
This is based on an example that was recently posted on llvm-dev: void *propagate_null(void* b, int* g) { if (!b) { return 0; } (*g)++; return b; } https://godbolt.org/g/xYk3qG The original code or constant propagation in other passes has obscured the fact that the phi can be removed completely. Differential Revision: https://reviews.llvm.org/D45448 llvm-svn: 329755
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Daniel Neilson authored
Summary: The verification rules for the intrinsics for atomic memcpy, atomic memmove, and atomic memset are basically code clones. This change merges their verification rules into a single block to remove duplication. llvm-svn: 329753
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Steven Wu authored
Summary: Darwin dynamic linker can handle weak symbols in ConstDataSection. ReadonReadOnlyWithRel symbols should be emitted in ConstDataSection instead of normal DataSection. rdar://problem/39298457 Reviewers: dexonsmith, kledzik Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D45472 llvm-svn: 329752
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Daniel Neilson authored
Summary: A simple refactor to remove duplicate code in the definitions of MemSetInst, AtomicMemSetInst, and AnyMemSetInst. Introduce a templated base class that contains all of the methods unique to a memset intrinsic, and derive these three classes from that. llvm-svn: 329747
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Jessica Paquette authored
Recommit r329716 "Add missing nullptr check before getSection() to AArch64MachObjectWriter::recordRelocation" This commit fixes the bot failures that were coming up before with r329716. The fix was to move the check for "isInSection()" inside of the if condition and emit the error there instead of waiting to get past the unreachable statement. This should work in debug and release builds now. llvm-svn: 329746
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Daniel Neilson authored
Summary: A simple refactor to remove duplicate code in the definitions of MemTransferInst, AtomicMemTransferInst, and AnyMemTransferInst. Introduce a templated base class that contains all of the methods unique to a memory transfer intrinsic, and derive these three classes from that. llvm-svn: 329744
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Amara Emerson authored
rdar://39175175 llvm-svn: 329743
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Gabor Buella authored
Reviewers: craig.topper, zvi, echristo Reviewed By: craig.topper Differential Revision: https://reviews.llvm.org/D45055 llvm-svn: 329742
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Sanjay Patel authored
llvm-svn: 329736
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Craig Topper authored
[X86] Change the name string for the newly add DF flag register to 'dirflag' to match the clobber name supported by clang for MS inline assembly. This should fix the failure found by Chromium reported here https://bugs.chromium.org/p/chromium/issues/detail?id=831158 The test case will be added in clang. llvm-svn: 329734
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Aaron Smith authored
llvm-svn: 329733
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Sanjay Patel authored
On 2nd reading, putting the C example after the bit about multiple regions makes this flow better. llvm-svn: 329732
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Robert Widmann authored
Summary: Noticed by Andrea Di Biagio while reviewing r329369 Reviewers: whitequark, harlanhaskins Reviewed By: harlanhaskins Subscribers: llvm-commits, abergmeier-dsfishlabs Differential Revision: https://reviews.llvm.org/D45496 llvm-svn: 329731
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Sanjay Patel authored
llvm-svn: 329729
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Jessica Paquette authored
Revert 329716 "Add missing nullptr check before getSection() to AArch64MachObjectWriter::recordRelocation" This broke a bunch of bots so I'm reverting while I figure it out. llvm-svn: 329728
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Sanjay Patel authored
This is copied from Andrea's text in PR36875: https://bugs.llvm.org/show_bug.cgi?id=36875 As noted there, this is a hack...but it's a good one! It's important to show potential workflows up-front with examples, so customers can copy and experiment with them. llvm-svn: 329726
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Aaron Smith authored
llvm-svn: 329724
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Jessica Paquette authored
There was a missing not line. Also, tail call before ret -> call before ret. llvm-svn: 329723
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Krzysztof Parzyszek authored
Delay printing the newline until after the opening bracket was printed, e.g. BUNDLE implicit-def $r1, implicit-def $r21, implicit $r1 { renamable $r1 = S2_asr_i_r renamable $r1, 1 renamable $r21 = A2_tfrsi 0 } instead of BUNDLE implicit-def $r1, implicit-def $r21, implicit $r1 { renamable $r1 = S2_asr_i_r renamable $r1, 1 renamable $r21 = A2_tfrsi 0 } llvm-svn: 329719
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Peter Collingbourne authored
Caused a build failure in check-tsan. llvm-svn: 329718
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Jessica Paquette authored
There was missing nullptr check before a call to getSection() in recordRelocation. This would result in a segfault in code like the attached test. This adds the missing check and a test which makes sure we get the expected error output. llvm-svn: 329716
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Nicolai Haehnle authored
Summary: We would like the UMR debugging tool[0] to be able to provide disassembly for currently live waves based on plain memory dumps, and we want to leverage the LLVM disassembler for this. This mostly works, except that UMR clearly can't provide real symbol info, so it wants to set DisInfo == nullptr. [0] https://cgit.freedesktop.org/amd/umr/ Reviewers: arsenm, rampitec, artem.tamazov, dp Subscribers: kzhuravl, wdng, yaxunl, dstuttard, tpr, t-tye, llvm-commits Differential Revision: https://reviews.llvm.org/D45477 Change-Id: Ibb2c5af2e66f2e100b4702fd81308e1932bc4ee6 llvm-svn: 329715
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Aaron Smith authored
llvm-svn: 329712
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Andrea Di Biagio authored
llvm-svn: 329711
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Chad Rosier authored
llvm-svn: 329709
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Andrea Di Biagio authored
[llvm-mca] Move the logic that prints dispatch unit statistics from BackendStatistics to its own view. This patch moves the logic that collects and analyzes dispatch events to the DispatchStatistics view. Added flag -dispatch-stats to print statistics related to the dispatch logic. llvm-svn: 329708
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Aaron Smith authored
llvm-svn: 329707
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Pavel Labath authored
Summary: This type is created on-demand and used as the base type for array ranges. Since it is "special", its construction did not go through the createTypeDIE function and so it was never inserted into the accelerator table, although it clearly belongs there. I add an explicit addAccelType call to insert it into the table. During review, we also decided to rename the type to something more unique to avoid confusion in case the user has own "sizetype" type. The new name for the type size __ARRAY_SIZE_TYPE__. Reviewers: JDevlieghere, aprantl, dblaikie Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D45445 llvm-svn: 329705
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Simon Pilgrim authored
llvm-svn: 329704
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Pavel Labath authored
Failed<ErrorInfoBase>() did not compile, because it was attempting to create a copy of the Error object when passing it to the nested matcher, which was not possible because ErrorInfoBase is abstract. This commit fixes the problem by making sure we pass the ErrorInfo object by reference, which also improves the handling of non-abstract objects, as we avoid potentially slicing an object during the copy. llvm-svn: 329703
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