Commits · 31adc28d24b1a95bb47df23068b6f61dfb5cd012 · Roger Ferrer / llvm-epi · GitLab

Aug 20, 2020
- GlobalISel: Implement fewerElementsVector for G_CONCAT_VECTORS sources · 31adc28d
  Matt Arsenault authored Aug 03, 2020
  31adc28d
Aug 19, 2020
- [AArch64][GlobalISel] Handle rtcGPR64RegClassID in... · e887d0e8
  Raul Tambre authored Aug 19, 2020
  e887d0e8
- [GlobalISel] Add combine for (x & mask) -> x when (x & mask) == x · d25b12bd
  Jessica Paquette authored Aug 06, 2020
  d25b12bd
- AMDGPU/GlobalISel: Add some bitcast tests · ff5758fe
  Matt Arsenault authored Aug 19, 2020
  
  ff5758fe
- AMDGPU/GlobalISel: Add selection tests for pointer constants · 386a5ea2
  Matt Arsenault authored Aug 18, 2020
  
  386a5ea2
- [X86][AVX] getAVX512TruncNode - don't truncate from illegal vector widths. · b61cef3a
  Simon Pilgrim authored Aug 19, 2020
  b61cef3a
- [ARM] Change target triple to arm-none-none-eabi. NFC · 41495dd5
  David Green authored Aug 19, 2020
  
  41495dd5
- [X86][AVX] computeKnownBitsForTargetNode - add VTRUNC/VTRUNCS/VTRUNCUS known... · 80a0dc59
  Simon Pilgrim authored Aug 19, 2020
  80a0dc59
- [SVE] Add tests for fixed length vector integer operations with immediate operands. · 08ba4f11
  Paul Walker authored Aug 18, 2020
  
  08ba4f11
- [X86][AVX] Fold store(extract_element(vtrunc)) to truncated store · 46fc9a0d
  Simon Pilgrim authored Aug 19, 2020
  46fc9a0d
- Revert "[AMDGPU] Support disassembly for AMDGPU kernel descriptors" · fdf71d48
  Ronak Chauhan authored Aug 19, 2020
  fdf71d48
- [SVE][CodeGen] Fix scalable vector issues in DAGTypeLegalizer::GenWidenVectorLoads · 3f36561f
  David Sherwood authored Aug 12, 2020
  3f36561f
- [AMDGPU] Support disassembly for AMDGPU kernel descriptors · cacfb02d
  Ronak Chauhan authored Jun 19, 2020
  cacfb02d
- AMDGPU: Implement waterfall loop for MIMG instructions with 256-bit SRsrc · e7081d11
  Changpeng Fang authored Aug 18, 2020
  e7081d11
Aug 18, 2020
- [AArch64][SVE] Add patterns for integer mla/mls. · be944c85
  Eli Friedman authored Aug 10, 2020
  be944c85
- [AArch64][SVE] Allow llvm.aarch64.sve.st2/3/4 with vectors of pointers. · bb185323
  Eli Friedman authored Aug 04, 2020
  bb185323
- [GlobalISel][CallLowering] Don't tail call with non-forwarded explicit sret · f29e6277
  Jessica Paquette authored Aug 18, 2020
  f29e6277
- GlobalISel: Implement fewerElementsVector for G_INSERT_VECTOR_ELT · 5a15f662
  Matt Arsenault authored Jul 27, 2020
  5a15f662
- [GlobalISel] Add a combine for sext_inreg(load x), c --> sextload x · 04a6ea5d
  Amara Emerson authored Aug 14, 2020
  04a6ea5d
- [GlobalISel] Add a combine for ashr(shl x, c), c --> sext_inreg x, c' · 40e269ea
  Amara Emerson authored Aug 14, 2020
  40e269ea
- [X86][AVX] lowerShuffleWithVPMOV - add non-VLX support. · 11ff5176
  Simon Pilgrim authored Aug 18, 2020
  11ff5176
- [ARM] Allow tail predication of VLDn · 3471520b
  David Green authored Aug 18, 2020
  3471520b
- [ARM] Use mov operand if the mov cannot be moved while tail predicating · 31f02ac6
  Sam Tebbs authored Aug 17, 2020
  31f02ac6
- [GlobalISel][CallLowering] Look through call parameters for flags · 224a8c63
  Jessica Paquette authored Aug 17, 2020
  224a8c63
- [XCOFF] emit .rename for .lcomm when necessary · f48eced3
  jasonliu authored Aug 18, 2020
  f48eced3
- [X86] Regenerate load-slice test labels. NFCI. · 87122c34
  Simon Pilgrim authored Aug 18, 2020
  87122c34
- [X86][AVX] lowerShuffleWithPERMV - pad 128/256-bit shuffles on non-VLX targets · abd33bf5
  Simon Pilgrim authored Aug 18, 2020
  abd33bf5
- [X86][AVX] lowerShuffleWithVTRUNC - extend to support v16i16/v32i8 binary shuffles. · 011bf4fd
  Simon Pilgrim authored Aug 18, 2020
  011bf4fd
- AMDGPU/GlobalISel: Select llvm.amdgcn.groupstaticsize · 2f5f5feb
  Matt Arsenault authored Jul 26, 2020
  2f5f5feb
- AMDGPU/GlobalISel: Fix selection of s1/s16 G_[F]CONSTANT · 3ba7777b
  Matt Arsenault authored Jul 25, 2020
  3ba7777b
- [SVE] Fix shift-by-imm patterns used by asr, lsl & lsr intrinsics. · 9f63dc32
  Paul Walker authored Aug 13, 2020
  9f63dc32
- [SVE] Lower fixed length vector ISD::SPLAT_VECTOR operations. · cb5cc47a
  Paul Walker authored Aug 17, 2020
  cb5cc47a
- [X86][AVX] Lower v16i8/v8i16 binary shuffles using VTRUNC/TRUNCATE · d2057a80
  Simon Pilgrim authored Aug 18, 2020
  d2057a80
- [Test][NFC] Add a new test to verify if scheduler can cluster two ld/st · 9b32ef94
  QingShan Zhang authored Aug 18, 2020
  9b32ef94
- [PowerPC] Implement Vector Extract Mask builtins in LLVM/Clang · c7ec3a7e
  Amy Kwan authored Aug 12, 2020
  c7ec3a7e
Aug 17, 2020
- [NVPTX] Fix typo in lit test · 33490acf
  Ellis Hoag authored Aug 17, 2020
  33490acf
- AMDGPU/GlobalISel: Match global saddr addressing mode · a9ee0589
  Matt Arsenault authored Aug 16, 2020
  
  a9ee0589
- AMDGPU: Match global saddr addressing mode · e1a2f471
  Matt Arsenault authored Aug 13, 2020
  e1a2f471
- AMDGPU: Add baseline tests for global saddr matching · 087dcbe9
  Matt Arsenault authored Aug 15, 2020
  
  087dcbe9
- [AMDGPU] Define spill opcodes for all AGPR sizes · 24182f14
  Stanislav Mekhanoshin authored Aug 17, 2020
  24182f14