llvm-svn: 272199

Summary:
Now DISubroutineType has a 'cc' field which should be a DW_CC_ enum.  If
it is present and non-zero, the backend will emit it as a
DW_AT_calling_convention attribute. On the CodeView side, we translate
it to the appropriate enum for the LF_PROCEDURE record.

I added a new LLVM vendor specific enum to the list of DWARF calling
conventions. DWARF does not appear to attempt to standardize these, so I
assume it's OK to do this until we coordinate with GCC on how to emit
vectorcall convention functions.

Reviewers: dexonsmith, majnemer, aaboud, amccarth

Subscribers: mehdi_amini, llvm-commits

Differential Revision: http://reviews.llvm.org/D21114

llvm-svn: 272197

llvm-svn: 272196

with user specified count has been applied.

Summary:
Previously SetLoopAlreadyUnrolled() set the disable pragma only if
there was some loop metadata.
Now it set the pragma in all cases. This helps to prevent multiple
unroll when -unroll-count=N is given.

Reviewers: mzolotukhin

Differential Revision: http://reviews.llvm.org/D20765

From: Evgeny Stupachenko <evstupac@gmail.com>
llvm-svn: 272195

This is the preparation patch to port the analysis to new PM

Differential Revision: http://reviews.llvm.org/D20560

llvm-svn: 272194

llvm-svn: 272193

Reviewers: iteratee

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D21087

llvm-svn: 272192

llvm-svn: 272191

Avoids unnecessary copies. All changes audited & pass tests with asan.
No functional change intended.

llvm-svn: 272190

Differential Revision: http://reviews.llvm.org/D21107

llvm-svn: 272187

It provides nothing over the default one but makes the class not
trivially copyable. No functionality change intended.

llvm-svn: 272186

MSVC calls the copy ctor on StratifiedSets for some reason. So,
undelete it.

llvm-svn: 272184

Again, the Microsoft linker does not like empty substreams.

We still emit an empty string table if CodeView is enabled, but that
doesn't cause problems because it always contains at least one null
byte.

llvm-svn: 272183

This is NFC as far as externally visible behavior is concerned, but will
keep us from spinning in the worklist traversal algorithm unnecessarily.

llvm-svn: 272182

Absence of may-unwind calls is not enough to guarantee that a
UB-generating use of an add-rec poison in the loop latch will actually
cause UB.  We also need to guard against calls that terminate the thread
or infinite loop themselves.

This partially addresses PR28012.

llvm-svn: 272181

Calls to `@llvm.dbg.*` can be assumed to terminate.

llvm-svn: 272180

The worklist algorithm introduced in rL271151 didn't check to see if the
direct users of the post-inc add recurrence propagates poison.  This
change fixes the problem and makes the code structure more obvious.

Note for release managers: correctness wise, this bug wasn't a
regression introduced by rL271151 -- the behavior of SCEV around
post-inc add recurrences was strictly improved (in terms of correctness)
in rL271151.

llvm-svn: 272179

llvm-svn: 272177

When repairing with a copy, instead of accounting for the cost of that
copy and actually inserting it, we may be able to use an alternative
source for the register to repair and just use it.

Make sure this is documented, so that we consider that opportunity at
some point.

llvm-svn: 272176

llvm-svn: 272174

r272064 apparently made them angry. This undoes some changes made in
r272064 (defaulting move ctors) to make them happy again.

llvm-svn: 272173

Reviewed By: ruiu
Differential Revision: http://reviews.llvm.org/D21128

llvm-svn: 272172

llvm-svn: 272171

Teach AArch64RegisterBankInfo that G_OR can be mapped on either GPR or
FPR for 64-bit or 32-bit values.

Add test cases demonstrating how this information is used to coalesce a
computation on a single register bank.

llvm-svn: 272170

The RegBankSelect pass can now rely on the target to do the remapping of
the instructions.

llvm-svn: 272169

The new version of the header introduces the INSTR_PROF_VISIBILITY
macro. See http://reviews.llvm.org/D21116 for more details.

llvm-svn: 272166

Now, the target will be able to provide its how implementation to remap
an instruction. This open the way to crazier optimizations, but to
beginning with, we will be able to handle something else than the
default mapping.

llvm-svn: 272165

Now that we have an entity that hold the remap information the
rewritting should be easier to do.

No functional changes.

llvm-svn: 272164

The repairing code has no reason to change the source or destination of
the registers.

llvm-svn: 272163

This helper class is used to encapsulate the necessary information
to remap an instruction.

llvm-svn: 272161

This G_OR is used in GlobalISel to represent bitwise OR.

llvm-svn: 272160

When the command line option is set, it overrides any thing that the
target may have set. The rationale is that we get what we asked for.

Options are respectively regbankselect-fast and regbankselect-greedy for
fast and greedy mode.

llvm-svn: 272158

repairing.

Copies are easy because we repair only when there is a mismatch. For
non-copy repairing, i.e., cases that involves breaking down or gathering
up the value, one of the operand may not have a register bank yet. Thus,
derivate a cost from that, requires more work.

llvm-svn: 272157

The MSR instructions can write to the CPSR, but we did not model this
fact, so we could emit them in the middle of IT blocks, changing the
condition flags for later instructions in the block.

The tests use two calls to llvm.write_register.i32 because it is valid
to use these instructions at the end of an IT block, which if conversion
does do in some cases. With two calls, the first clobbers the flags, so
a branch has to be used to make the second one conditional.

Differential Revision: http://reviews.llvm.org/D21139

llvm-svn: 272154

llvm-svn: 272147

The architecture enumeration is shared across ARM and AArch64.  However, the
data is not.  The code incorrectly would index into the array using the
architecture index which was offset by the ARMv7 architecture enumeration.  We
do not have a marker for indicating the architectural family to which the
enumeration belongs so we cannot be clever about offsetting the index (at least
it is not immediately apparent to me).  Instead, fall back to the tried-and-true
method of slowly iterating the array (its not a large array, so the impact of
this is not too high).

Because of the incorrect indexing, if we were lucky, we would crash, but usually
we would return an invalid StringRef.  We did not have any tests for the AArch64
target parser previously;.  Extend the previous tests I had added for ARM to
cover AArch64 for ensuring that we return expected StringRefs.

Take the opportunity to change some iterator types to references.

This work is needed to support parsing `.arch name` directives in the AArch64
target asm parser.

llvm-svn: 272145

llvm-svn: 272140

llvm-svn: 272139

llvm-svn: 272138

Also, switch to using functions from LiveIntervalAnalysis to update
live intervals, instead of performing the updates manually.

Re-committing r272045.

llvm-svn: 272135