Commits · 3d7df0a547b3ed81cc920cf8ab9a3724348468b3 · Roger Ferrer / llvm-epi · GitLab

Sep 27, 2023
- [RISCV][CostModel] Estimate cost of Extract/InsertElement with non-constant... · 3d7df0a5
  Sergey Kachkov authored Sep 27, 2023
  3d7df0a5
- [LoopUnroll] Store more information in UnrollCostEstimator (NFCI) · 296671f0
  Nikita Popov authored Sep 27, 2023
  296671f0
- [ConstraintElim] Add A < B if A is an increasing phi for A != B. · e6a1657f
  Florian Hahn authored Sep 27, 2023
  e6a1657f
- [LoopIterator] Add const qualifier to LoopInfo (NFC) · 0c77171d
  Nikita Popov authored Sep 27, 2023
  0c77171d
- [AArch64] Enable "sink-and-fold" in MachineSink by default (#67432) · ace20e24
  Momchil Velikov authored Sep 27, 2023
  
  ace20e24
- Revert "[NVPTX] Add support for maxclusterrank in launch_bounds (#66496)" · 0afbcb20
  Sam McCall authored Sep 27, 2023
  0afbcb20
- [ScheduleDAG] Fix false assert target · 13c603a4
  lennyxiao authored Sep 27, 2023
  13c603a4
- [DSE] Only query object size for identified objects · 7aab12e1
  Nikita Popov authored Sep 27, 2023
  7aab12e1
- [InstCombine] Canonicalize phi order for newly inserted nodes · 2fda200c
  Nikita Popov authored Sep 26, 2023
  2fda200c
- [RISCV] Remove duplicate pattern in RISCVInstrInfoVPseudos.td (#67436) · 2153eb37
  Brandon Wu authored Sep 27, 2023
  
  2153eb37
- [RISCV] Support select/merge like ops for fp16 vectors when only have Zvfhmin · 5278cc36
  Jianjian GUAN authored Aug 29, 2023
  5278cc36
- [NVPTX] Add support for maxclusterrank in launch_bounds (#66496) · dfab31b4
  Jakub Chlanda authored Sep 27, 2023
  dfab31b4
- [RISCV] Support fmaximum/fminimum for fp16 vector when only Zvfhmin enabled (#67393) · d6b1b998
  Jim Lin authored Sep 27, 2023
  d6b1b998
- [TableGen] Enhance !range bang operator (#66489) · df330d74
  Pengcheng Wang authored Sep 27, 2023
  df330d74
- [RISCV] Promote SETCC and VP_SETCC of f16 vectors when only have zvfhmin (#66866) · 435da4ef
  Jianjian GUAN authored Sep 27, 2023
  435da4ef
- [RISCV] Remove unused isSEWAware, NFC (#67411) · abd0fab1
  Jianjian GUAN authored Sep 27, 2023
  
  abd0fab1
- Revert "[Coverage] Allow Clang coverage to be used with debug info correlation." · 4d5d9a53
  Zequan Wu authored Sep 26, 2023
  4d5d9a53
- [TargetLowering] fix index OOB (#67494) · 35a364fa
  Nick Desaulniers authored Sep 26, 2023
  35a364fa
Sep 26, 2023
- [LLParser] Merge xor constantexpr parsing with add/mul/shl/lshr/ashr. (#67371) · 8c26e473
  Craig Topper authored Sep 26, 2023
  8c26e473
- [DebugInfo] Change return type of DWARFDebugAbbrev::parse (#67191) · 32e10aa6
  Alex Langford authored Sep 26, 2023
  32e10aa6
- [DebugMetadata][DwarfDebug] Support function-local types in lexical block scopes (4/7) · f8aab289
  Vladislav Dzhidzhoev authored Jul 18, 2023
  f8aab289
- [SLP]Do not gather node, if the instruction, that does not require · ea7f43ec
  Alexey Bataev authored Sep 20, 2023
  ea7f43ec
- [RISCV] Correct Zhinx load/store patterns to use AddrRegImm. · b26157ed
  Craig Topper authored Sep 26, 2023
  
  b26157ed
- [X86] Move IsNOT helper after getTargetConstantBitsFromNode helper. NFC. · 715bed66
  Simon Pilgrim authored Sep 26, 2023
  715bed66
- [RISCV] Disable constant hoisting for mul by one more/less than a pow… (#67385) · 64b1fbb3
  Craig Topper authored Sep 26, 2023
  64b1fbb3
- [RISCV] Update comment on -w stripping pass. NFC (#67415) · 733e3c60
  Luke Lau authored Sep 26, 2023
  733e3c60
- [AArch64] Bail out of HomogeneousPrologEpilog for functions with swif… (#67417) · baf39032
  Zhaoxuan Jiang authored Sep 26, 2023
  baf39032
- [RA] Don't split a register generated from another split (#67351) · 31f81e96
  weiguozhi authored Sep 26, 2023
  31f81e96
- [RISCV] Explicitly create IMPLICIT_DEF instead of UNDEF for vectors i… (#67369) · 65eb4687
  Craig Topper authored Sep 26, 2023
  65eb4687
- [llvm-cxxfilt] Do not consider the prefix dot as part of the demangled symbol name. · 1ff958c3
  zhijian authored Sep 26, 2023
  1ff958c3
- [RISCV] Transform build_vector((binop X_i, C_i)..) to binop (build_vector, build_vector) (#67358) · e39add89
  Philip Reames authored Sep 26, 2023
  e39add89
- [Bitcode] Add some missing GetTypeByID failure checks · c2515a8f
  Nikita Popov authored Sep 26, 2023
  c2515a8f
- [AArch64] Handle scalable vectors in combineFMulOrFDivWithIntPow2. · 03647e2e
  David Green authored Sep 26, 2023
  03647e2e
- [SPIRV] Add OpAccessChain instruction support (#66253) · c01b5bbb
  Nathan Gauër authored Sep 26, 2023
  c01b5bbb
- [AMDGPU] Fix passing CodeGen/AMDGPU/frem.ll on gfx1150. (#67425) · 64482d57
  Ivan Kosarev authored Sep 26, 2023
  64482d57
- [AMDGPU] Remove the support for non-True16 copies between different register sizes. · 287f6cdd
  Ivan Kosarev authored Jul 21, 2023
  287f6cdd
- [PowerPC] A fix for D159073. Do not optimize when register classes are different in src and dst. · f2f61a99
  esmeyi authored Sep 26, 2023
  f2f61a99
- [MachineLICM] Handle Subloops · ff68e43c
  Jingu Kang authored Jul 20, 2023
  ff68e43c
- [AArch64] Limit immediate offsets when folding instructions into addressing modes (#67345) · fe763d8a
  Momchil Velikov authored Sep 26, 2023
  fe763d8a
- [TargetLowering] use stable_sort to avoid nondeterminism · 679c3a17
  Sam McCall authored Sep 26, 2023
  679c3a17