Commits · 5fa289f0d8ff85b9e14d2f814a90761378ab54ae · Roger Ferrer / llvm-epi · GitLab

May 22, 2017
- [AMDGPU] Narrow lshl from 64 to 32 bit if possible · 5fa289f0
  Stanislav Mekhanoshin authored May 22, 2017
  5fa289f0
- [AMDGPU] Fix incorrect register usage tracking in GCNUpwardTracker · 74cb9c88
  Valery Pykhtin authored May 22, 2017
  74cb9c88
- [mips] Support micromips attribute passed by front-end · e0b726f2
  Simon Atanasyan authored May 22, 2017
  e0b726f2
- Re-apply r302416: [ARM] Clear the constant pool cache on explicit .ltorg directives · 6110be97
  James Molloy authored May 22, 2017
  6110be97
- [MIPS] Add support to match more patterns for DINS instruction · ab9573f3
  Strahinja Petrovic authored May 22, 2017
  ab9573f3
- Revert "[ARM] Clear the constant pool cache on explicit .ltorg directives" · 5cc75ae8
  James Molloy authored May 22, 2017
  5cc75ae8
May 21, 2017
- [GlobalISel][X86] Fix G_TRUNC instruction selection. · 014fc566
  Igor Breger authored May 21, 2017
  014fc566
- Summary · 37e63b1b
  Hiroshi Inoue authored May 21, 2017
  37e63b1b
May 19, 2017
- [AMDGPU][MC] Corrected disassembler to decode instructions with 2 literals · ce941c9c
  Dmitry Preobrazhensky authored May 19, 2017
  ce941c9c
- [AMDGPU][MC] Fixed bugs in export instruction · 9321e8fc
  Dmitry Preobrazhensky authored May 19, 2017
  9321e8fc
- [X86][AVX512] Make i1 illegal in the CodeGen · 548e22a1
  Guy Blank authored May 19, 2017
  548e22a1
- [globalisel][tablegen] Demote OptForSize/OptForMinSize/ForCodeSize to per-function predicates. · a1b2db79
  Daniel Sanders authored May 19, 2017
  a1b2db79
May 18, 2017
- Revert r302938 "Add LiveRangeShrink pass to shrink live range within BB." · b00ffd8c
  Hans Wennborg authored May 18, 2017
  b00ffd8c
- [IR] De-virtualize ~Value to save a vptr · 96ab8726
  Reid Kleckner authored May 18, 2017
  96ab8726
- [LegacyPassManager] Remove TargetMachine constructors · 8b61764c
  Francis Visoiu Mistrih authored May 18, 2017
  8b61764c
- [AMDGPU] SDWA operands should not intersect with potential MIs · ebfdaf73
  Sam Kolton authored May 18, 2017
  ebfdaf73
- [GlobalISel][X86] G_ADD/G_SUB vector legalizer/selector support. · 842b5b36
  Igor Breger authored May 18, 2017
  842b5b36
- [X86][AVX512] Add 512-bit vector ctpop costs + tests · 6bba6068
  Simon Pilgrim authored May 18, 2017
  6bba6068
- [X86] Replace slow LEA instructions in X86 · 2ea271b5
  Lama Saba authored May 18, 2017
  2ea271b5
- [Target/X86] Remove unneeded return. NFCI. · 9ae69a75
  Davide Italiano authored May 18, 2017
  9ae69a75
May 17, 2017
- AMDGPU: Start defining a calling convention · 2b1f9aa5
  Matt Arsenault authored May 17, 2017
  2b1f9aa5
- CodeGen: Power: Add lowering for shifts of v1i128. · f6c61ef6
  Kyle Butt authored May 17, 2017
  f6c61ef6
- Fix PR33028 · ab129846
  Michael Liao authored May 17, 2017
  ab129846
- AMDGPU: Expand frame indexes to be relative to scratch wave offset · 2525e4e4
  Matt Arsenault authored May 17, 2017
  2525e4e4
- AMDGPU: Change mubuf soffset register when SP relative · 156d3ae0
  Matt Arsenault authored May 17, 2017
  156d3ae0
- [X86][AVX512] Add 512-bit vector ctlz costs + tests · 23ef2672
  Simon Pilgrim authored May 17, 2017
  23ef2672
- AMDGPU: Make better use of op_sel with high components · 98f2946a
  Matt Arsenault authored May 17, 2017
  98f2946a
- [X86][AVX512] Add 512-bit vector cttz costs + tests · d0365967
  Simon Pilgrim authored May 17, 2017
  d0365967
- Only enable LiveRangeShrink for x86. · 02828a93
  Dehao Chen authored May 17, 2017
  02828a93
- AMDGPU: Try to use op_sel when selecting packed instructions · 786eeea2
  Matt Arsenault authored May 17, 2017
  786eeea2
- [WebAssembly][NFC] Update expected testsuite failures for newly passing tests · c63fb00f
  Jacob Gravelle authored May 17, 2017
  c63fb00f
- AMDGPU: Use appropriate soffset for spilling · ea8a4ed5
  Matt Arsenault authored May 17, 2017
  ea8a4ed5
- AMDGPU: Fix min3/max3 combines for f16/i16 · ee324ffc
  Matt Arsenault authored May 17, 2017
  ee324ffc
- [X86][AVX512] Add 512-bit vector bitreverse costs + tests · a9a92a1a
  Simon Pilgrim authored May 17, 2017
  a9a92a1a
- [PPC] Properly update register save area offsets · 2b053312
  Krzysztof Parzyszek authored May 17, 2017
  2b053312
- [GlobalISel][X86] Support add i64 in IA32. · 28f290fa
  Igor Breger authored May 17, 2017
  28f290fa
- [SystemZ] Modelling of costs of divisions with a constant power of 2. · 8722ade7
  Jonas Paulsson authored May 17, 2017
  8722ade7
- Reland r303247: [ARM] GlobalISel: Remove dead instruction selection code · eafa4aa9
  Diana Picus authored May 17, 2017
  eafa4aa9
- Revert "[ARM] GlobalISel: Remove dead instruction selection code" · 36e4ba0f
  Diana Picus authored May 17, 2017
  36e4ba0f
- [ARM] GlobalISel: Remove dead instruction selection code · 68d21c86
  Diana Picus authored May 17, 2017
  68d21c86