Commits · a428b5afbd6d48edda9d21ffabd57eee1e7b984d · Roger Ferrer / llvm-epi · GitLab

Jul 28, 2023
- [Object] Use COFF archive format for import libraries. · bacc7aeb
  Jacek Caban authored Jul 27, 2023
  bacc7aeb
- [Object] [NFC] Use llvm::COFF::is64Bit in COFF import file implementation. · 6b04ec1d
  Jacek Caban authored Jul 27, 2023
  6b04ec1d
- Revert "[RISCV] Add support for XCVbi extension in CV32E40P" · e4777dc4
  melonedo authored Jul 28, 2023
  e4777dc4
- [AArch64] Add funnel shift lowering for SelectionDAG · 8eeabf67
  Tuan Chuong Goh authored Jul 28, 2023
  8eeabf67
- Revert "[RISCVRVVInitUndef] Remove implicit single use assumption for IMPLICIT_DEF" · d5f496a2
  Kevin Athey authored Jul 28, 2023
  d5f496a2
- [ARM] Correctly handle combining segmented stacks with execute-only · 8336d38b
  John Brawn authored Jul 25, 2023
  8336d38b
- [RISCV] Add support for XCVbi extension in CV32E40P · bf2ad26b
  melonedo authored Jun 25, 2023
  bf2ad26b
- [RISCV][MC] Implement mapping symbols · a0d8a53c
  Job Noorman authored Jul 28, 2023
  a0d8a53c
- [RISCV][MC] Relax conditional branches to unresolved symbols · 856745c5
  Job Noorman authored Jul 28, 2023
  856745c5
- [RISCV] Add support for XCVsimd extension in CV32E40P · 3c0604b2
  melonedo authored Jun 11, 2023
  3c0604b2
- [RISCV][MC] Add CLI option to disable branch relaxation · afb2e9f4
  Job Noorman authored Jul 28, 2023
  afb2e9f4
- [RISCV] Remove some instructions from Zvfbfwma by implying Zfbfmin according to the latest spec · e56bf133
  Jun Sha (Joshua) authored Jul 28, 2023
  e56bf133
- [X86] Support -march=arrowlake,arrowlake-s,lunarlake · c9d92e66
  Freddy Ye authored Jul 28, 2023
  c9d92e66
- [RISCV] Add support for XCValu extension in CV32E40P · 092e60a3
  Qihan Cai authored Jul 20, 2023
  092e60a3
- [RISCV] Add codegen support for bf16 vector · 2b6df4a3
  Jun Sha (Joshua) authored Jul 28, 2023
  2b6df4a3
- [JITLink] Don't try to abandon non-existent allocations. · b3c0055c
  Lang Hames authored Jul 27, 2023
  b3c0055c
- [RISCVRVVInitUndef] Remove implicit single use assumption for IMPLICIT_DEF · 9cf67592
  Philip Reames authored Jul 27, 2023
  9cf67592
- [SLP][PR64099]Fix unsound undef to poison transformation when handling · 48bc5b0a
  Alexey Bataev authored Jul 27, 2023
  48bc5b0a
- [llvm-profdata] Refactoring Sample Profile Reader to increase FDO build speed... · 66ba71d9
  William Huang authored Jul 12, 2023
  66ba71d9
- [WebAssembly][Objcopy] Write output section headers identically to inputs · 1b21067c
  Derek Schuff authored Jul 25, 2023
  1b21067c
- [InstCombine] Folding `@llvm.ptrmask` with itself · edf2e0e0
  Noah Goldstein authored Jul 27, 2023
  edf2e0e0
- [AMDGPU] Avoid CodeGen dependencies from AMDGPU/Utils and MCTargetDesc · f86c81b2
  Reid Kleckner authored Jul 26, 2023
  f86c81b2
Jul 27, 2023
- [AArch64] Switch magic numbers to library functions in fixup · f1c21fae
  Daniel Hoekwater authored Jul 27, 2023
  f1c21fae
- Revert "[FuncSpec] Add Phi nodes to the InstCostVisitor." · 32683b23
  Douglas Yung authored Jul 27, 2023
  32683b23
- Adjust includes in MCTargetDesc to avoid unnecessary CodeGen deps, NFC · f6909cff
  Reid Kleckner authored Jul 26, 2023
  f6909cff
- Adjust includes in MCTargetDesc to avoid unnecessary CodeGen deps, NFC · 2d03b7c5
  Reid Kleckner authored Jul 26, 2023
  2d03b7c5
- Upgrade a rdar://5907648 link to a github issue · 3e0cdf33
  Jon Roelofs authored Jul 27, 2023
  3e0cdf33
- Upgrade a rdar://8459039 link to a github issue · 80fae88a
  Jon Roelofs authored Jul 27, 2023
  80fae88a
- ExecutionEngine: support `IMAGE_REL_AMD64_SECTION` relocations · d4a5bef1
  Saleem Abdulrasool authored Jul 27, 2023
  d4a5bef1
- [AArch64][Windows] Fix the slot offset of the swift async context register. · a90228b9
  Hiroshi Yamauchi authored Jul 26, 2023
  a90228b9
- [RISCV] Rename timm5 to tsimm5 to better reflect that it is a signed immediate. · 3046fb6d
  Craig Topper authored Jul 27, 2023
  
  3046fb6d
- [RISCV] When using vror.vi for left rotate, mask the inverted immediate to SEW. · a81e1f0f
  Craig Topper authored Jul 27, 2023
  a81e1f0f
- [FuncSpec] Add Phi nodes to the InstCostVisitor. · 96ff464d
  Alexandros Lamprineas authored Jul 27, 2023
  96ff464d
- [AArch64] [XRay] Account for XRay event instrs in Branch Relaxation · 3435a6a0
  Daniel Hoekwater authored Jul 21, 2023
  3435a6a0
- A new code layout algorithm for function reordering [2/3] · bc59faa8
  spupyrev authored Jun 13, 2023
  bc59faa8
- [RISCV] Add EmitPriority=0 to Zcb load/store aliases with no immediate offset. · aad360d6
  Craig Topper authored Jul 27, 2023
  aad360d6
- [CostModel][X86] Add scalar rotate-by-immediate costs · bbfdb8cc
  Simon Pilgrim authored Jul 27, 2023
  bbfdb8cc
- [AggressiveInstCombine] Fold strcmp for short string literals with size 2 · cbfcf901
  Maksim Kita authored Jul 27, 2023
  cbfcf901
- [TextAPI] Update missing enum cases & utility functions · 27459a3a
  Cyndy Ishida authored Jul 26, 2023
  27459a3a
- [InstCombine] Explicitly track dead edges · 70aca7b1
  Nikita Popov authored Jul 27, 2023
  70aca7b1