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  1. Mar 23, 2017
  2. Mar 22, 2017
  3. Mar 21, 2017
    • Matt Arsenault's avatar
      AMDGPU: Remove hasSideEffects from SI_RETURN_TO_EPILOG · 513cb7a8
      Matt Arsenault authored
      llvm-svn: 298454
      513cb7a8
    • Matt Arsenault's avatar
      AMDGPU: Rename SI_RETURN · 5b20fbb7
      Matt Arsenault authored
      This is used for a specific type of return to a shader part's
      epilog code. Rename to try avoiding confusion from a true
      call's return.
      
      llvm-svn: 298452
      5b20fbb7
    • George Burgess IV's avatar
      Let llvm.objectsize be conservative with null pointers · 56c7e88c
      George Burgess IV authored
      This adds a parameter to @llvm.objectsize that makes it return
      conservative values if it's given null.
      
      This fixes PR23277.
      
      Differential Revision: https://reviews.llvm.org/D28494
      
      llvm-svn: 298430
      56c7e88c
    • Coby Tayree's avatar
      [X86][MS-compatability][llvm] allow MS TYPE/SIZE/LENGTH operators as a part of... · 07a8974c
      Coby Tayree authored
      [X86][MS-compatability][llvm] allow MS TYPE/SIZE/LENGTH operators as a part of a compound expression
      
      This patch introduces X86AsmParser with the ability to handle the aforementioned ops within compound "MS" arithmetical expressions.
      Currently - only supported as a stand alone Operand, e.g.:
      "TYPE X"
      now allowed :
      "4 + TYPE X * 128"
      
      Clang side: https://reviews.llvm.org/D31174
      
      Differential Revision: https://reviews.llvm.org/D31173
      
      llvm-svn: 298425
      07a8974c
    • Davide Italiano's avatar
      [X86] Remove extra semicolon to placate GCC. NFCI. · 200e5e18
      Davide Italiano authored
      llvm-svn: 298423
      200e5e18
    • Artyom Skrobov's avatar
      [ARM] Recommit the glueless lowering of addc/adde in Thumb1, · 40a4f406
      Artyom Skrobov authored
      including the amended (no UB anymore) fix for adding/subtracting -2147483648.
      
      This reverts r298328 "[ARM] Revert r297443 and r297820."
      and partially reverts r297842 "Revert "[Thumb1] Fix the bug when adding/subtracting -2147483648""
      
      llvm-svn: 298417
      40a4f406
    • Krzysztof Parzyszek's avatar
      Recommit r298282 with fixes for memory allocation/deallocation · d033d1fd
      Krzysztof Parzyszek authored
      [Hexagon] Recognize polynomial-modulo loop idiom again
      
      Regain the ability to recognize loops calculating polynomial modulo
      operation. This ability has been lost due to some changes in the
      preceding optimizations. Add code to preprocess the IR to a form
      that the pattern matching code can recognize.
      
      llvm-svn: 298400
      d033d1fd
    • Marek Olsak's avatar
      AMDGPU: Buffer descriptor changes for GFX9 · 5c7a61d2
      Marek Olsak authored
      Reviewers: arsenm
      
      Subscribers: qcolombet, kzhuravl, wdng, nhaehnle, yaxunl, tony-tye, dstuttard, tpr
      
      Differential Revision: https://reviews.llvm.org/D31158
      
      llvm-svn: 298397
      5c7a61d2
    • Marek Olsak's avatar
      AMDGPU: Always use VGPR indexing on GFX9 · e22fdb9c
      Marek Olsak authored
      Reviewers: arsenm
      
      Subscribers: kzhuravl, wdng, nhaehnle, yaxunl, tony-tye, dstuttard, tpr
      
      Differential Revision: https://reviews.llvm.org/D31157
      
      llvm-svn: 298396
      e22fdb9c
    • Reid Kleckner's avatar
      Rename AttributeSet to AttributeList · b518054b
      Reid Kleckner authored
      Summary:
      This class is a list of AttributeSetNodes corresponding the function
      prototype of a call or function declaration. This class used to be
      called ParamAttrListPtr, then AttrListPtr, then AttributeSet. It is
      typically accessed by parameter and return value index, so
      "AttributeList" seems like a more intuitive name.
      
      Rename AttributeSetImpl to AttributeListImpl to follow suit.
      
      It's useful to rename this class so that we can rename AttributeSetNode
      to AttributeSet later. AttributeSet is the set of attributes that apply
      to a single function, argument, or return value.
      
      Reviewers: sanjoy, javed.absar, chandlerc, pete
      
      Reviewed By: pete
      
      Subscribers: pete, jholewinski, arsenm, dschuff, mehdi_amini, jfb, nhaehnle, sbc100, void, llvm-commits
      
      Differential Revision: https://reviews.llvm.org/D31102
      
      llvm-svn: 298393
      b518054b
    • Matt Arsenault's avatar
      AMDGPU: Fix not including v2i16/v2f16 in register class · 5af82a7a
      Matt Arsenault authored
      llvm-svn: 298390
      5af82a7a
    • Matt Arsenault's avatar
      AMDGPU: Fix asserting on 0 dmask for image intrinsics · f8fb605a
      Matt Arsenault authored
      Fold these to undef during lowering so users get eliminated.
      
      llvm-svn: 298387
      f8fb605a
    • Sanne Wouda's avatar
      [ARM] [Assembler] Support negative immediates for A32, T32 and T16 · 2409c640
      Sanne Wouda authored
      Summary:
      To support negative immediates for certain arithmetic instructions, the
      instruction is converted to the inverse instruction with a negated (or inverted)
      immediate. For example, "ADD r0, r1, #FFFFFFFF" cannot be encoded as an ADD
      instruction.  However, "SUB r0, r1, #1" is equivalent.
      
      These conversions are different from instruction aliases.  An alias maps
      several assembler instructions onto one encoding.  A conversion, however, maps
      an *invalid* instruction--e.g. with an immediate that cannot be represented in
      the encoding--to a different (but equivalent) instruction.
      
      Several instructions with negative immediates were being converted already, but
      this was not systematically tested, nor did it cover all instructions.
      
      This patch implements all possible substitutions for ARM, Thumb1 and
      Thumb2 assembler and adds tests.  It also adds a feature flag
      (-mattr=+no-neg-immediates) to turn these substitutions off.  This is
      helpful for users who want their code to assemble to exactly what they
      wrote.
      
      Reviewers: t.p.northover, rovka, samparker, javed.absar, peter.smith, rengolin
      
      Reviewed By: javed.absar
      
      Subscribers: aadg, aemerson, llvm-commits
      
      Differential Revision: https://reviews.llvm.org/D30571
      
      llvm-svn: 298380
      2409c640
    • Sanjay Patel's avatar
      [x86] use PMOVMSK for vector-sized equality comparisons · 79379cae
      Sanjay Patel authored
      We could do better by splitting any oversized type into whatever vector size the target supports, 
      but I left that for future work if it ever comes up. The motivating case is memcmp() calls on 16-byte
      structs, so I think we can wire that up with a TLI hook that feeds into this.
      
      Differential Revision: https://reviews.llvm.org/D31156
      
      llvm-svn: 298376
      79379cae
    • Valery Pykhtin's avatar
      fd4c410f
    • Sam Kolton's avatar
      [ADMGPU] SDWA peephole optimization pass. · f60ad58d
      Sam Kolton authored
      Summary:
      First iteration of SDWA peephole.
      
      This pass tries to combine several instruction into one SDWA instruction. E.g. it converts:
      '''
          V_LSHRREV_B32_e32 %vreg0, 16, %vreg1
          V_ADD_I32_e32 %vreg2, %vreg0, %vreg3
          V_LSHLREV_B32_e32 %vreg4, 16, %vreg2
      '''
      Into:
      '''
         V_ADD_I32_sdwa %vreg4, %vreg1, %vreg3 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
      '''
      
      Pass structure:
          1. Iterate over machine instruction in basic block and try to apply "SDWA patterns" to each of them. SDWA patterns match machine instruction into either source or destination SDWA operand. E.g. ''' V_LSHRREV_B32_e32 %vreg0, 16, %vreg1''' is matched to source SDWA operand '''%vreg1 src_sel:WORD_1'''.
          2. Iterate over found SDWA operands and find instruction that could be potentially coverted into SDWA. E.g. for source SDWA operand potential instruction are all instruction in this basic block that uses '''%vreg0'''
          3. Iterate over all potential instructions and check if they can be converted into SDWA.
          4. Convert instructions to SDWA.
      
      This review contains basic implementation of SDWA peephole pass. This pass requires additional testing fot both correctness and performance (no performance testing done).
      There are several ways this pass can be improved:
          1. Make this pass work on whole function not only basic block. As I can see this can be done right now without changes to pass.
          2. Introduce more SDWA patterns
          3. Introduce mnemonics to limit when SDWA patterns should apply
      
      Reviewers: vpykhtin, alex-t, arsenm, rampitec
      
      Subscribers: wdng, nhaehnle, mgorny
      
      Differential Revision: https://reviews.llvm.org/D30038
      
      llvm-svn: 298365
      f60ad58d
    • Andrea Di Biagio's avatar
      [DebugInfo][X86] Teach Optimize LEAs pass to handle debug values · 7937be7d
      Andrea Di Biagio authored
      This patch fixes an issue in the Optimize LEAs pass where redundant LEAs were
      not removed because they were being used by debug values. The debug values are
      now ignored when determining whether LEAs are redundant.
      
      For now the debug values for the redundant LEAs are marked as undefined,
      effectively lost. The intention is for a follow up patch which will attempt to
      preserve the debug values where possible.
      
      Patch by Andrew Ng.
      
      Differential Revision: https://reviews.llvm.org/D30835
      
      llvm-svn: 298360
      7937be7d
    • Jonas Paulsson's avatar
      [SystemZ] Don't drop MO flags in foldMemoryOperandImpl() · bd65421f
      Jonas Paulsson authored
      The def operand of the new LG/LD should have the old def operands
      flags and subreg index.
      
      New test: test/CodeGen/SystemZ/fold-memory-op-impl.ll
      
      Review: Ulrich Weigand
      llvm-svn: 298341
      bd65421f
    • Vitaly Buka's avatar
      Revert "[Hexagon] Recognize polynomial-modulo loop idiom again" · c12716e7
      Vitaly Buka authored
      Fix memory leaks on check-llvm tests detected by Asan.
      
      This reverts commit r298282.
      
      llvm-svn: 298329
      c12716e7
    • Eli Friedman's avatar
      [ARM] Revert r297443 and r297820. · 76732acc
      Eli Friedman authored
      The glueless lowering of addc/adde in Thumb1 has known serious
      miscompiles (see https://reviews.llvm.org/D31081), and r297820
      causes an infinite loop for certain constructs.  It's not
      clear when they will be fixed, so let's just take them out
      of the tree for now.
      
      (I resolved a small conflict with r297453.)
      
      llvm-svn: 298328
      76732acc
  4. Mar 20, 2017
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