Commits · b5871dfaf31873e6172f8a3fcd1e01e54498c811 · Roger Ferrer / llvm-epi · GitLab

Jul 21, 2022
- [AMDGPU][MC][NFC] Refine SMEM load definitions. · 4b9dbbdb
  Ivan Kosarev authored Jul 21, 2022
  4b9dbbdb
- [AMDGPU][NFC] Validate G_MERGE_VALUES as we match zero-extended 32-bit scalars. · 75950be8
  Ivan Kosarev authored Jul 21, 2022
  75950be8
- AMDGPU: Refine user-sgpr-init16-bug · 5a5439cb
  Matt Arsenault authored Jul 20, 2022
  5a5439cb
- [AMDGPU] Combine s_or_saveexec, s_xor instructions. · fd64a857
  Thomas Symalla authored Jun 29, 2022
  fd64a857
- [AArch64][SVE] Add DAG-Combine to push bitcasts from floating point loads after DUPLANE128 · cd3d7bf1
  Matt Devereau authored Jul 18, 2022
  cd3d7bf1
- [AArch64][SVE] Add ISel pattern to lower DUPLANE128 to LD1RQD · e0fbd990
  Matt Devereau authored Jul 12, 2022
  e0fbd990
- [AMDGPU][GlobalISel] Fix subtarget checks for combining to v_med3_i16 · 9383b098
  Jay Foad authored Jul 21, 2022
  9383b098
- [CSKY] Fix the testcase error due to the verifyInstructionPredicates · 08db0891
  Zi Xuan Wu (Zeson) authored Jul 21, 2022
  08db0891
- [RISCV] Combine (select_cc (srl (and X, 1<<C), C), 0, eq/ne, true, fale) · add17fc8
  Craig Topper authored Jul 20, 2022
  add17fc8
- [RISCV] Refactor the common combines for SELECT_CC and BR_CC into a helper function. · 7dda6c71
  Craig Topper authored Jul 20, 2022
  7dda6c71
- [RISCV] Optimize (brcond (seteq (and X, 1 << C), 0)) · 8983db15
  Craig Topper authored Jul 20, 2022
  8983db15
- [RISCV] Recognize bexti from (srl (and X, 1<<C), C). · 31b8939d
  Craig Topper authored Jul 20, 2022
  31b8939d
Jul 20, 2022
- [NFC] Suppress unused variable warning in non-assert builds · bc9b964f
  Arthur Eubanks authored Jul 20, 2022
  
  bc9b964f
- [AMDGPU] NFC. Assert that mask is full with VOPC DPP · dc850fbf
  Joe Nash authored Jul 19, 2022
  dc850fbf
- [ARM] Fix Thumb2 compare being emitted ExpandCMP_SWAP · 4704da13
  David Green authored Jul 20, 2022
  4704da13
- Reland "[AArch64] Add a tablegen pattern for UZP2." · 051738b0
  Alexandros Lamprineas authored Jul 18, 2022
  051738b0
- [LoopVectorize][AArch64] Add TTI hook preferPredicatedReductionSelect · 79660d33
  David Sherwood authored Jul 14, 2022
  79660d33
- Use value instead of getValue (NFC) · 0387da6f
  Kazu Hirata authored Jul 19, 2022
  
  0387da6f
- [X86] Make sure load size is not larger than stack slot · d946fb8d
  Haohai Wen authored Jul 20, 2022
  d946fb8d
- [AArch64] Use SUBXrx64 for dynamic stack to refer to sp · d337c1f2
  chenglin.bi authored Jul 20, 2022
  d337c1f2
- Use has_value instead of hasValue (NFC) · 41ae78ea
  Kazu Hirata authored Jul 19, 2022
  
  41ae78ea
- [x86] use zero-extending load of a byte outside of loops too (2nd try) · f0dd12ec
  Sanjay Patel authored Jul 19, 2022
  f0dd12ec
Jul 19, 2022
- Revert "[x86] use zero-extending load of a byte outside of loops too" · 95401b01
  Sanjay Patel authored Jul 19, 2022
  95401b01
- [Attributor] Replace AAValueSimplify with AAPotentialValues · bf789b19
  Johannes Doerfert authored Jun 21, 2022
  bf789b19
- [x86] use zero-extending load of a byte outside of loops too · 9d1ea177
  Sanjay Patel authored Jul 19, 2022
  9d1ea177
- [SystemZ][z/OS] Introduce CCAssignToRegAndStack to calling convention · 6fb27bc2
  Yusra Syeda authored Jul 19, 2022
  6fb27bc2
- [amdgpu] Implement lds kernel id intrinsic · 3a205977
  Jon Chesterfield authored Jul 19, 2022
  3a205977
- [nfc][amdgpu] LDS. Move selection logic up the stack. · 2224bbcd
  Jon Chesterfield authored Jul 19, 2022
  
  2224bbcd
- [AMDGPU] Remove old operand from VOPC DPP · b28bb8cc
  Joe Nash authored Jul 15, 2022
  b28bb8cc
- [ARM] Remove VBICimm if no cleared bits are demanded · 6cb95290
  David Green authored Jul 19, 2022
  6cb95290
- [DAG] SimplifyDemandedBits - relax "xor (X >> ShiftC), XorC --> (not X) >>... · 0f6b0461
  Simon Pilgrim authored Jul 19, 2022
  0f6b0461
- [AMDGPU] Set amdgpu-memory-bound if a basic block has dense global memory access · 9fa425c1
  Abinav Puthan Purayil authored Jul 13, 2022
  9fa425c1
- [llvm][AArch64] Add missing FPCR, H and B registers to Codeview mapping · 5d148732
  David Spickett authored Jul 14, 2022
  5d148732
- [AArch64] Add patterns to fold zext(cmpeq(x, splat(0))) · f7b2d4aa
  Cullen Rhodes authored Jul 19, 2022
  f7b2d4aa
- [AArch64][SVE] Fold fadda(ptrue, x, select(mask, y, -0.0)) into fadda(mask, x, y) · 05d424d1
  Rosie Sumpter authored Jul 12, 2022
  05d424d1
- [X86] Promote v32f16's fadd into v32f32's fadd when it is avx512 without avx512fp16 · e01bf5a3
  Bing1 Yu authored Jul 19, 2022
  e01bf5a3
- [VE] Support load/store/spill of vector mask registers · 469044cf
  Kazushi (Jam) Marukawa authored Jul 02, 2022
  469044cf
- [AArch64][NFC] Set true for default of subfeature is more readable · bddf2073
  zhongyunde authored Jul 19, 2022
  bddf2073
- [RISCV][Clang] Add support for Zmmul extension · 3198364e
  ksyx authored Jun 25, 2022
  3198364e
Jul 18, 2022
- CodeGen: Remove AliasAnalysis from regalloc · 8d0383eb
  Matt Arsenault authored Jun 24, 2022
  8d0383eb