Commits · cb6b2565f5265d8f1e014c2feb88df657bf5d674 · Roger Ferrer / llvm-epi · GitLab

Jan 26, 2023
- [AArch64][SME2] Add multi-vector saturating doubling multiply high intrinsics · cb6b2565
  Kerry McLaughlin authored Jan 26, 2023
  cb6b2565
- [AMDGPU] sendmsg(MSG_ORDERED_PS_DONE) is not supported on GFX11 · a420ba95
  Jay Foad authored Jan 25, 2023
  a420ba95
- [SystemZ] Use llvm::countl_zero and llvm::countr_zero (NFC) · 7510b7ec
  Kazu Hirata authored Jan 25, 2023
  7510b7ec
- Use llvm::Log2_32 and llvm::Log2_64 instead of llvm::findLastSet (NFC) · a5cd202e
  Kazu Hirata authored Jan 25, 2023
  a5cd202e
- [Mips] Simplify loadImmediate (NFC) · cdc2a047
  Kazu Hirata authored Jan 25, 2023
  cdc2a047
- [Mips] Simplify isShiftedUIntAtAnyPosition (NFC) · 3b53c602
  Kazu Hirata authored Jan 25, 2023
  3b53c602
- [RISCV] Rename CS_ALU tablegen class to CA_ALU. NFC · 8de27543
  Craig Topper authored Jan 25, 2023
  8de27543
Jan 25, 2023
- [AMDGPU] Remove predicates from real dot instructions. NFCI. · ccdd4ae1
  Stanislav Mekhanoshin authored Jan 25, 2023
  ccdd4ae1
- [AMDGPU] Make flat_offset a 32-bit operand instead of 16-bits · f84d3dd0
  Mateja Marjanovic authored Jan 25, 2023
  f84d3dd0
- Fix warnings · c4c5e79d
  Kazu Hirata authored Jan 25, 2023
  c4c5e79d
- [AArch64] Remove HasCrypto tablegen predicate. NFC · bbe352d8
  David Green authored Jan 25, 2023
  bbe352d8
- [SVE][InstrFormats] Explcitly set hasSideEffects for all SVE instructions. · 9394088c
  Paul Walker authored Jan 19, 2023
  9394088c
- [AArch64] Codegen for FEAT_LRCPC3 · 7c84f94e
  Tomas Matheson authored Jan 25, 2023
  7c84f94e
- [AArch64] Codegen for FEAT_LSE128 · f1f58334
  Tomas Matheson authored Jan 25, 2023
  f1f58334
- [AArch64][SME2] Add intrinsics to move multi-vectors to/from ZA. · 5f3dab09
  Kerry McLaughlin authored Jan 25, 2023
  5f3dab09
- [AArch64][SME2] Add Multi-vector add/sub and accumulate into ZA intrinsic · 03aed959
  Caroline Concatto authored Jan 25, 2023
  03aed959
- [AArch64][SME2] Add the IR intrinsics for SME2 fclamp, sclamp and uclamp instructions · c5e9d577
  David Sherwood authored Jan 23, 2023
  c5e9d577
- [AMDGPU][MC][NFC] MUBUF code cleanup · cefc8428
  Piotr Sobczak authored Jan 25, 2023
  cefc8428
- [llvm] Use llvm::bit_ceil instead of PowerOf2Ceil (NFC) · 22cdc6a1
  Kazu Hirata authored Jan 25, 2023
  22cdc6a1
- [X86] Use llvm::countr_zero instead of findFirstSet (NFC) · 5d346216
  Kazu Hirata authored Jan 24, 2023
  5d346216
- [SystemZ] Use llvm::bit_floor (NFC) · d5248a46
  Kazu Hirata authored Jan 24, 2023
  d5248a46
- [M68k][MC] Make immediate operands relocatable · b3de3164
  Min Hsu authored Oct 10, 2022
  b3de3164
- [M68k][Disassembler] Use custom decoder for 32-bit immediates · c40b158e
  Min Hsu authored Nov 20, 2022
  c40b158e
- [RISCV] Combine extract_vector_elt followed by VFMV_S_F_VL. · b7166e25
  Craig Topper authored Jan 24, 2023
  b7166e25
Jan 24, 2023
- [X86] Add support for "light" AVX · d7043e8c
  Ilya Tokar authored Dec 15, 2022
  d7043e8c
- IR: Add atomicrmw uinc_wrap and udec_wrap · 778cf543
  Matt Arsenault authored Nov 02, 2022
  778cf543
- [MC] Store target Insts table in reverse order. NFC. · 96f49905
  Jay Foad authored Jan 11, 2023
  96f49905
- [AArch64] Add the Ampere1A core · fb0af891
  Philipp Tomsich authored Jan 24, 2023
  fb0af891
- [AArch64] Update enabled extensions for Ampere1 core · 8dfbf8d1
  Philipp Tomsich authored Jan 24, 2023
  8dfbf8d1
- [RISCV][LSR] Treat number of instructions as dominate factor in LSR cost decisions · a9871772
  Philip Reames authored Jan 24, 2023
  a9871772
- [AMDGPU] Split dot8 feature · 870b9297
  Stanislav Mekhanoshin authored Jan 23, 2023
  870b9297
- [AVR] Support most address space casts · 8202a3da
  Ayke van Laethem authored Jan 19, 2023
  8202a3da
- [SVE] Fix invalid INSERT_SUBVECTOR creation when lowering fixed length fp-int conversions. · 3f94a383
  Paul Walker authored Jan 21, 2023
  3f94a383
- [NFC] Deprecate DataLayout::getPrefTypeAlignment · 89427bb7
  Guillaume Chatelet authored Jan 24, 2023
  
  89427bb7
- [AArch64][SME2] Add Multi-vector add/sub, storing into ZA intrinsic · a582a059
  Caroline Concatto authored Jan 24, 2023
  a582a059
- [NFC] Deprecate SelectionDag functions taking Alignment as unsigned · 355cc3fd
  Guillaume Chatelet authored Jan 24, 2023
  
  355cc3fd
- [RISCV] Combine FP_TO_INT to vfwcvt/fvncvt · f5a64471
  Luke Lau authored Jan 19, 2023
  f5a64471
- [NFC] Deprecate SelectionDag::getLoad that takes alignment as · 8b1d86ae
  Guillaume Chatelet authored Jan 23, 2023
  8b1d86ae
- [AArch64][SME2] Add Multi-vector saturating extract narrow and interleave intrinsics · 06191d13
  Caroline Concatto authored Jan 23, 2023
  06191d13
- [AMDGPU] Add missing physical register check in SIFoldOperands::tryFoldLoad · 2a832d0f
  Yashwant Singh authored Jan 24, 2023
  2a832d0f