Commits · d03df8145f3b84d51dcb0c37053bfb7dbb69669f · Roger Ferrer / llvm-epi · GitLab

Dec 20, 2016
- [ARM] Implement isExtractSubvectorCheap. · d03df814
  Eli Friedman authored Dec 20, 2016
  d03df814
- [ARM] Generate checks for shuffle tests using update_llc_test_checks.py. · 7ce3d799
  Eli Friedman authored Dec 20, 2016
  7ce3d799
- AMDGPU: Allow 16-bit types in inline asm constraints · 9e910142
  Matt Arsenault authored Dec 20, 2016
  9e910142
- AMDGPU: Run fp combine tests on VI · d1ceffcd
  Matt Arsenault authored Dec 20, 2016
  d1ceffcd
- AMDGPU: Don't add same instruction multiple times to worklist · 4c1e9ec0
  Matt Arsenault authored Dec 20, 2016
  4c1e9ec0
- AMDGPU/SI: Add a MachineMemOperand when lowering llvm.amdgcn.buffer.load.* · 6f9ef14b
  Tom Stellard authored Dec 20, 2016
  6f9ef14b
- AMDGPU/SI: Add a MachineMemOperand to MIMG instructions · 244891d1
  Tom Stellard authored Dec 20, 2016
  244891d1
- [IR] Remove the DIExpression field from DIGlobalVariable. · bceaaa96
  Adrian Prantl authored Dec 20, 2016
  bceaaa96
- Add ARM support to update_llc_test_checks.py · 1a9a887a
  Eli Friedman authored Dec 19, 2016
  1a9a887a
Dec 19, 2016
- [AMDGPU] When unifying metadata, add operands to named metadata individually · 980688cd
  Konstantin Zhuravlyov authored Dec 19, 2016
  980688cd
- [ARM] GlobalISel: Add more checks to test · 3bae486b
  Diana Picus authored Dec 19, 2016
  3bae486b
- [ARM] GlobalISel: Minor style fixup in test · 58265c47
  Diana Picus authored Dec 19, 2016
  58265c47
- [ARM] GlobalISel: Lower i8 and i16 register args · 97ae95c3
  Diana Picus authored Dec 19, 2016
  97ae95c3
- [ARM] GlobalISel: Allow i8 and i16 adds · 5a724452
  Diana Picus authored Dec 19, 2016
  5a724452
- [ARM] GlobalISel: Select i8 and i16 copies · 36aa09fa
  Diana Picus authored Dec 19, 2016
  36aa09fa
- [ARM] GlobalISel: Lower more than 4 arguments · 1437f6d7
  Diana Picus authored Dec 19, 2016
  1437f6d7
- [ARM] GlobalISel: Support loading from the stack · 519807f7
  Diana Picus authored Dec 19, 2016
  519807f7
- [XRay] Fix assertion failure on empty machine basic blocks (PR 31424) · 03b8be57
  Dean Michael Berris authored Dec 19, 2016
  03b8be57
Dec 18, 2016
- Revert r289955 and r289962. This is causing lots of ASAN failures for us. · 373f9a6a
  Daniel Jasper authored Dec 18, 2016
  373f9a6a
- [X86][SSE] Add support for combining target shuffles to SHUFPS. · e940daf5
  Simon Pilgrim authored Dec 18, 2016
  e940daf5
- [X86][SSE][AVX-512] Convert FAND/FOR/FXOR/FANDN nodes to integer operations if... · 7029db0e
  Craig Topper authored Dec 18, 2016
  7029db0e
- [AVX-512] Use EVEX encoded XOR instruction for zeroing scalar registers when... · add9cc69
  Craig Topper authored Dec 18, 2016
  add9cc69
- [AVX-512] Make sure VLX is also enabled before using EVEX encoded logic ops... · 2baef8f4
  Craig Topper authored Dec 18, 2016
  2baef8f4
Dec 17, 2016
- AMDGPU: Fix broken check prefix in test · 3aaf11fb
  Matt Arsenault authored Dec 17, 2016
  3aaf11fb
- [AVX-512] Use EVEX encoded logic operations for scalar types when they are... · d3295c6a
  Craig Topper authored Dec 17, 2016
  d3295c6a
- [AVX-512] Update scalar logic test to show missed opportunity to use EVEX... · 81b021e7
  Craig Topper authored Dec 17, 2016
  81b021e7
- Revert "AArch64CollectLOH: Rewrite as block-local analysis." · 15b56e69
  Matthias Braun authored Dec 17, 2016
  15b56e69
- Move test to correct directory · 9439d3dc
  Matthias Braun authored Dec 17, 2016
  9439d3dc
- AArch64CollectLOH: Rewrite as block-local analysis. · e813cf45
  Matthias Braun authored Dec 17, 2016
  e813cf45
- AArch64: Enable post-ra liveness updates · 76bb4139
  Matthias Braun authored Dec 16, 2016
  76bb4139
Dec 16, 2016
- [CodeGenPrep] Skip merging empty case blocks · 90b6b507
  Jun Bum Lim authored Dec 16, 2016
  90b6b507
- Revert "[IR] Remove the DIExpression field from DIGlobalVariable." · 73ec0656
  Adrian Prantl authored Dec 16, 2016
  73ec0656
- [ARM] Add ARMISD::VLD1DUP to match vld1_dup more consistently. · f624ec27
  Eli Friedman authored Dec 16, 2016
  f624ec27
- Revert "[CodeGenPrep] Skip merging empty case blocks" · f9416af1
  Jun Bum Lim authored Dec 16, 2016
  f9416af1
- [X86] Fold (setcc (cmp (atomic_load_add x, -C) C), COND) to (setcc (LADD x, -C), COND) (PR31367) · 35f21cba
  Hans Wennborg authored Dec 16, 2016
  35f21cba
- [CodeGenPrep] Skip merging empty case blocks · 85347dde
  Jun Bum Lim authored Dec 16, 2016
  85347dde
- [X86][AVX512] use a single shufps for 512-bit vectors when it can save instructions · 9519bd92
  Simon Pilgrim authored Dec 16, 2016
  9519bd92
- [X86][AVX512] Add tests showing missed opportunity to efficiently lower v16i32 to VSHUFPS (PR27885) · 224416a9
  Simon Pilgrim authored Dec 16, 2016
  224416a9
- [ARM] GlobalISel: Select add i32, i32 · 812caee6
  Diana Picus authored Dec 16, 2016
  812caee6
- [X86][SSE] Combine shuffles to MOVSS/MOVSD whatever the domain. · f159a341
  Simon Pilgrim authored Dec 16, 2016
  f159a341