Commits · d056d5decfb593cfc53b421a89075d2063f76ec9 · Roger Ferrer / llvm-epi · GitLab

Feb 19, 2021
- [RISCV] Use custom isel for vector indexed load/store intrinsics. · d056d5de
  Craig Topper authored Feb 19, 2021
  d056d5de
- [RISCV] Prevent selecting a 0 VL to X0 for the segment load/store intrinsics. · dbf910f0
  Craig Topper authored Feb 19, 2021
  dbf910f0
- [RISCV] Move SHFLI matching to DAG combine. Add 32-bit support for RV64 · 98dff5e8
  Craig Topper authored Feb 19, 2021
  98dff5e8
- [SampleFDO] Add PromotedInsns to prevent repeated ICP. · 4ffad1fb
  Wei Mi authored Feb 19, 2021
  4ffad1fb
- [AArch64][GlobalISel] Run redundant_sext_inreg in the post-legalizer combiner · 8d3442ed
  Jessica Paquette authored Feb 17, 2021
  8d3442ed
- [LV] Fold single-use variable into assert. NFC. · 59f442e6
  Benjamin Kramer authored Feb 19, 2021
  
  59f442e6
- [MemCopyOpt] Enable MemorySSA by default · 71a8e4e7
  Nikita Popov authored Jan 10, 2021
  71a8e4e7
- [SCEV] Use both known bits and sign bits when computing range of SCEV unknowns · 4a5edea1
  Philip Reames authored Feb 19, 2021
  4a5edea1
- [NFC][Regalloc] Share the VirtRegAuxInfo object with LiveRangeEdit · 82492f24
  Mircea Trofin authored Feb 17, 2021
  82492f24
- Make fixed-abi default for AMD HSA OS · 3c297a25
  madhur13490 authored Feb 10, 2021
  3c297a25
- [ARM] Correct vector predicate type in MVE getCmpSelInstrCost · a1c34a9d
  David Green authored Feb 19, 2021
  
  a1c34a9d
- [DAG] visitTRUNCATE - attempt to truncate USUBSAT · 5d3930bb
  Simon Pilgrim authored Feb 19, 2021
  5d3930bb
- Revert "[ARM] Expand the range of allowed post-incs in load/store optimizer" · 7a5c26e9
  David Green authored Feb 19, 2021
  7a5c26e9
- [LV] Remove VPCallback. · edc92a1c
  Florian Hahn authored Feb 19, 2021
  edc92a1c
- [RISCV] Address some clang-tidy warnings. NFCI. · d9531a30
  Fraser Cormack authored Feb 19, 2021
  
  d9531a30
- [AMDGPU] WQM/WWM: Fix marking of partial definitions · 8181dcd3
  Carl Ritson authored Feb 19, 2021
  8181dcd3
- [DCE] Don't remove non-willreturn calls · 2f17ed29
  Nikita Popov authored Feb 18, 2021
  2f17ed29
- [X86][AVX] getFauxShuffleMask - decode VBROADCAST(EXTRACT_VECTOR_ELT(V,0)) · 2258b367
  Simon Pilgrim authored Feb 19, 2021
  2258b367
- [IR] Move willReturn() to Instruction · 370addb9
  Nikita Popov authored Feb 18, 2021
  370addb9
- [BasicAA] Add simple depth limit to avoid stack overflow (PR49151) · 1d9f4903
  Nikita Popov authored Feb 18, 2021
  1d9f4903
- [X86] Fix a codegen crash in getSetCCResultType · c98644c2
  Wang, Pengfei authored Feb 19, 2021
  c98644c2
- [AArch64] Add some missing Neoverse features · 260f90bb
  Sjoerd Meijer authored Feb 18, 2021
  260f90bb
- [NPM][LTO] Do not enable MemorySSA with LoopFullUnrollPass · c141c655
  David Green authored Feb 19, 2021
  c141c655
- Reland "[Debugify] Make the debugify aware of the original (-g) Debug Info" · 1a2b3536
  Djordje Todorovic authored Feb 18, 2021
  1a2b3536
- [RISCV] Prune unneeded indexed load/store pseudo instructions. · cd4051ac
  Craig Topper authored Feb 18, 2021
  cd4051ac
- [CodeGen] Use range-based for loops (NFC) · fd04f3a3
  Kazu Hirata authored Feb 18, 2021
  
  fd04f3a3
- [Support] Use static_assert instead of assert (NFC) · 2d5eb672
  Kazu Hirata authored Feb 18, 2021
  2d5eb672
- [FPEnv][AArch64] Implement lowering of llvm.set.rounding · 2c4f60e4
  Serge Pavlov authored Feb 16, 2021
  2c4f60e4
- [ORC] Print CPU feature string in JITTargetMachineBuilder debugging output. · 0469256d
  Lang Hames authored Feb 19, 2021
  
  0469256d
- [Coroutine] Relax CoroElide musttail check · 3bf8f162
  Xun Li authored Feb 18, 2021
  3bf8f162
- [RISCV] Split zvlsseg searchable table into 4 separate tables. Index by... · 8ed3bbbc
  Craig Topper authored Feb 18, 2021
  8ed3bbbc
- [RISCV] Enable PrimaryKeyEarlyOut on RISCVVPseudosTable. · cf345591
  Craig Topper authored Feb 18, 2021
  cf345591
- Reset the EntryValue location flag in finalizeEntryValue. · c4ad878a
  Adrian Prantl authored Feb 18, 2021
  c4ad878a
- [SampleFDO] Stop repeated indirect call promotion for the same target. · 5fb65c02
  Wei Mi authored Feb 12, 2021
  5fb65c02
- MIR: Fix parser crash on syntax error on first character · 2d3d2e78
  Matt Arsenault authored Feb 18, 2021
  2d3d2e78
- [dfsan] Instrument origin variable and function definitions · 7e658b2f
  Jianzhou Zhao authored Feb 18, 2021
  7e658b2f
- [llvm][IR] Do not place constants with static relocations in a mergeable section · c77659e5
  Leonard Chan authored Feb 10, 2021
  c77659e5
Feb 18, 2021
- [CSSPGO] Use callsite sample counts to annotate indirect call sites. · e87b1b1d
  Hongtao Yu authored Feb 18, 2021
  e87b1b1d
- [Coverage] Store compilation dir separately in coverage mapping · 5fbd1a33
  Petr Hosek authored Feb 10, 2021
  5fbd1a33
- GlobalISel: Merge some AMDGPU ABI lowering code to generic code · 62d946e1
  Matt Arsenault authored Feb 07, 2021
  62d946e1