Commits · d44cd1bbeb7542eba06401279e5f2c117247019b · Roger Ferrer / llvm-epi · GitLab

Oct 13, 2022
- Revert "[FunctionAttrs] Make location classification more precise" · d44cd1bb
  Nikita Popov authored Oct 13, 2022
  d44cd1bb
- [ARM] Support fp16/bf16 using w constraint · 7d15212b
  Archibald Elliott authored Oct 11, 2022
  7d15212b
- [FunctionAttrs] Make location classification more precise · b05f5b90
  Nikita Popov authored Oct 13, 2022
  b05f5b90
- [ConstraintElim] Bail out for GEPs when index size > 64 bits. · 359bc5c5
  Florian Hahn authored Oct 13, 2022
  359bc5c5
- [FunctionAttrs] Handle potential access of captured argument · 440ce05f
  Nikita Popov authored Oct 13, 2022
  440ce05f
- Propagate tied operands when copying a MachineInstr. · 526ce9c9
  Simon Tatham authored Oct 13, 2022
  526ce9c9
- [FunctionAttrs] Account for memory effects of inalloca/preallocated · 5b377684
  Nikita Popov authored Oct 12, 2022
  5b377684
- [MC] [Win64EH] Check that ARM64 prologs and epilogs have the right matching number of instructions · cbd84645
  Martin Storsjö authored Aug 08, 2022
  cbd84645
- [AArch64] Use encodeLogicalImmediate for forming the immediate to an AND. NFC. · 24303e3a
  Martin Storsjö authored Oct 13, 2022
  24303e3a
- [AArch64] Remove dead code for inserting SEH opcodes for realignment. NFC. · 19e2b403
  Martin Storsjö authored Oct 12, 2022
  19e2b403
- [AArch64] Fix aligning the stack after calling __chkstk · 50e0aced
  Martin Storsjö authored Oct 11, 2022
  50e0aced
- AMDGPU: Fix assertion on <1 x i16> vectors · 838fd611
  Matt Arsenault authored Oct 12, 2022
  838fd611
- AMDGPU: Fix hazard with v_accvgpr_write_b32 and inline asm VGPR defs · 575eed3d
  Matt Arsenault authored Oct 11, 2022
  575eed3d
- [Hexagon] Switch vunpackub->op->vpackeb pattern to vzb/vshuffeb · 79632163
  Krzysztof Parzyszek authored Oct 10, 2022
  79632163
Oct 12, 2022
- [MC] Consider IsMTETaggedFrame in CIEKey · 42cdec11
  Florian Mayer authored Oct 10, 2022
  42cdec11
- [MC] Also sort on IsBKeyFrame · ab25678c
  Florian Mayer authored Oct 10, 2022
  ab25678c
- [RISCV] Use branchless form for selects with 0 in either arm · 1c41d0cb
  Philip Reames authored Oct 12, 2022
  1c41d0cb
- [Hexagon] Handle packing of even/odd 32-bit words · dca7e451
  Krzysztof Parzyszek authored Oct 12, 2022
  dca7e451
- Move interpreter check before modifying the allocation type. · 17095dfe
  Jacob Hegna authored Oct 12, 2022
  
  17095dfe
- [MLGO] Force persistency in tflite buffers. · 9d93a98f
  Jacob Hegna authored Oct 12, 2022
  9d93a98f
- [Hexagon] Implement TLI::isExtractSubvectorCheap hook · 2d8d2bec
  Krzysztof Parzyszek authored Oct 12, 2022
  
  2d8d2bec
- [ConstraintElim] Move GEP decomposition code to separate fn (NFC). · 0ebd2883
  Florian Hahn authored Oct 12, 2022
  0ebd2883
- [AArch64] Generate SEH info for PAC instructions · bd3fa318
  Martin Storsjö authored Oct 01, 2022
  bd3fa318
- [AArch64] [SEH] Rename pac_sign_return_address to pac_sign_lr · 918f6f58
  Martin Storsjö authored Oct 12, 2022
  918f6f58
- [llvm-objcopy] Support --decompress-debug-sections when zlib is disabled · e18b7c7a
  Fangrui Song authored Oct 12, 2022
  e18b7c7a
- [PrintPipeline] Handle CoroConditionalWrapper and add more verification · f59e1bcc
  Arthur Eubanks authored Oct 11, 2022
  f59e1bcc
- [SelectionDAG] Use consistent type sizes for opcode · 8b8463ef
  Mirko Brkusanin authored Oct 12, 2022
  
  8b8463ef
- [InstCombine] fold sdiv with common shl amount in operands · 7b9482df
  Sanjay Patel authored Oct 12, 2022
  7b9482df
- [SLP]Fix insertpoint of the extractellements instructions to avoid reshuffle crash. · d71ad410
  Alexey Bataev authored Oct 10, 2022
  d71ad410
- [InstCombine] fold udiv with common shl amount in operands · 008a8903
  Sanjay Patel authored Oct 12, 2022
  008a8903
- [NFC] Ignore unused var in no-asserts builds · cbae57c0
  Jordan Rupprecht authored Oct 12, 2022
  
  cbae57c0
- [SLP]Fix PR58177: Improve isUndefVector function to avoid extra freeze. · 1be3428e
  Alexey Bataev authored Oct 06, 2022
  1be3428e
- [LoongArch] Handle missing CondCodes · ec2640bf
  gonglingqin authored Oct 12, 2022
  ec2640bf
- [InstCombine] propagate "exact" through folds of div · fe97f950
  Sanjay Patel authored Oct 12, 2022
  fe97f950
- [InstCombine] add helper function for div+shl folds; NFC · d117ee25
  Sanjay Patel authored Oct 12, 2022
  d117ee25
- [LoongArch] Add earlyclobber of destination register to atomic instructions · b1d7a95e
  gonglingqin authored Oct 12, 2022
  b1d7a95e
- [VPlan] Remove dead recipes before sinking. · c1fe52bf
  Florian Hahn authored Oct 12, 2022
  c1fe52bf
- [NFC] Perform all legality checks for non-trivial unswitch in one function · fbad5fdc
  Max Kazantsev authored Oct 12, 2022
  fbad5fdc
- Don't widen shuffle element with AVX512 · f885c080
  Luo, Yuanke authored Oct 12, 2022
  f885c080
- Revert "[AArch64] Add support for 128-bit non temporal loads." · 1e723b7a
  David Green authored Oct 12, 2022
  1e723b7a