Commits · d779ee152ceff1fd52b3530014a6b10bbaa2d4b7 · Roger Ferrer / llvm-epi · GitLab

Mar 21, 2020
- [X86] getTargetShuffleAndZeroables - add insert_subvector(undef, sub, c) handling. · 25eb9056
  Simon Pilgrim authored Mar 21, 2020
  25eb9056
- [X86] Combine concat(shufps,shufps) -> shufps(concat,concat) · 4ceade04
  Simon Pilgrim authored Mar 21, 2020
  4ceade04
- Revert rGe6a7e3b5e3e7 "[X86][SSE] matchShuffleWithSHUFPD - add support for unary shuffles." · f424d51c
  Simon Pilgrim authored Mar 21, 2020
  f424d51c
- Fix Wdocumentation warning. NFCI. · ff3aae69
  Simon Pilgrim authored Mar 21, 2020
  
  ff3aae69
- [X86] Reland D71360 Clean up UseInitArray initialization for X86ELFTargetObjectFile · 85c30f33
  Fangrui Song authored Mar 19, 2020
  85c30f33
- Temporarily Revert "[X86] Reland D71360 Clean up UseInitArray initialization... · fc7233d7
  Eric Christopher authored Mar 20, 2020
  fc7233d7
Mar 20, 2020
- [VE] Fix -Wunused-private-field after D72598 and -Wdeprecated-declarations after D76348 · df4cc35e
  Fangrui Song authored Mar 20, 2020
  
  df4cc35e
- [X86] Reland D71360 Clean up UseInitArray initialization for X86ELFTargetObjectFile · 7899fe9d
  Fangrui Song authored Mar 19, 2020
  7899fe9d
- [X86] Prevent (bitcast (broadcast_load)) combine from producing vXf16 broadcast instructions. · 32fbea15
  Craig Topper authored Mar 20, 2020
  32fbea15
- [ARM,MVE] Add ACLE intrinsics for the vaddv/vaddlv family. · 1adfa4c9
  Simon Tatham authored Mar 20, 2020
  1adfa4c9
- [ARM,MVE] Add ACLE intrinsics for the vminv/vmaxv family. · 45a9945b
  Simon Tatham authored Mar 20, 2020
  45a9945b
- AMDGPU: Move towards deprecating alignbit intrinsic · a950e3be
  Matt Arsenault authored Mar 19, 2020
  a950e3be
- [AMDGPU] Enable divergence driven ISel for ADD/SUB i64 · 6e34e718
  alex-t authored Mar 19, 2020
  6e34e718
- [ARM,CDE] Implement CDE unpredicated Q-register intrinsics · 969034b8
  Mikhail Maltsev authored Mar 20, 2020
  969034b8
- [ARM,CDE] Implement CDE S and D-register intrinsics · d22e6617
  Mikhail Maltsev authored Mar 20, 2020
  d22e6617
- [ARM,CDE] Implement GPR CDE intrinsics · 7a85e358
  Mikhail Maltsev authored Mar 20, 2020
  7a85e358
- Revert "[TableGen][GlobalISel] Account for HwMode in RegisterBank register sizes" · baa6f6a7
  Adrian Kuegel authored Mar 20, 2020
  baa6f6a7
- [ARM] Change VDUP type to i32 for MVE · b3499f57
  David Green authored Mar 20, 2020
  b3499f57
- [RISCV] Select +0.0 immediate using fmv.{w,d}.x / fcvt.d.w · 3c24aee7
  Roger Ferrer authored Mar 20, 2020
  3c24aee7
- [AMDGPU] Reuse register during frame index elimination · 2cbb8c94
  Austin Kerbow authored Mar 18, 2020
  2cbb8c94
- [AMDGPU] Set the CostPerUse value for vgpr registers. · 728b878d
  cdevadas authored Mar 19, 2020
  728b878d
- Revert "Generate Callee Saved Register (CSR) related cfi directives like .cfi_restore." · a035726e
  Wei Mi authored Mar 19, 2020
  a035726e
- [WebAssembly] Support swiftself and swifterror for WebAssembly target · 08670d43
  Yuta Saito authored Mar 19, 2020
  08670d43
- [WebAssembly] SIMD integer abs instructions · 34db3c3a
  Thomas Lively authored Mar 18, 2020
  34db3c3a
- [WebAssembly] SIMD bitmask intrinsics and builtin functions · a3f974f3
  Thomas Lively authored Mar 18, 2020
  a3f974f3
- AMDGPU/GlobalISel: Remove leftover #if 0 · 678da7b1
  Matt Arsenault authored Mar 19, 2020
  678da7b1
Mar 19, 2020
- [MC][ARM] add implicit immediate form for ldrsbt/ldrht/ldrsht · f8756366
  Stefan Agner authored Mar 01, 2020
  f8756366
- [AMDGPU] Move frame pointer from s34 to s33 · 0e9368cc
  Scott Linder authored Mar 03, 2020
  0e9368cc
- [AMDGPU] Add Scratch Wave Offset to Scratch Buffer Descriptor in entry functions · 60b1967c
  Scott Linder authored Jan 21, 2020
  60b1967c
- [AMDGPU][NFC] Refactor some uses of unsigned to Register · db099f99
  Scott Linder authored Mar 11, 2020
  db099f99
- [AMDGPU][NFC] Refactor emitEntryFunctionPrologue · 30bb113b
  Scott Linder authored Feb 24, 2020
  30bb113b
- [AArch64][SVE] Add support for DestructiveBinaryImm DestructiveInstType · 018dde4c
  Cameron McInally authored Mar 19, 2020
  018dde4c
- [X86] Attempt to more accurately model the cost of a bool reduction of wide vector type. · c13aa36b
  Craig Topper authored Mar 19, 2020
  c13aa36b
- Reland D73534: [DebugInfo] Enable the debug entry values feature by default · d9b96210
  Djordje Todorovic authored Mar 19, 2020
  d9b96210
- [AArch64][SVE] Rename intrinsics for gather prefetch [NFC] · 0ea4fb5b
  Andrzej Warzynski authored Mar 19, 2020
  0ea4fb5b
- [PowerPC] implement target hook isProfitableToHoist · 3f85134d
  Chen Zheng authored Mar 19, 2020
  3f85134d
- [PowerPC] add IR level isFMAFasterThanFMulAndFAdd - NFC · aacf022c
  Chen Zheng authored Mar 18, 2020
  aacf022c
Mar 18, 2020
- Remove CompositeType class. · e24e95fe
  Eli Friedman authored Mar 03, 2020
  e24e95fe
- [TableGen][GlobalISel] Account for HwMode in RegisterBank register sizes · e9f22fd4
  lewis-revill authored Mar 18, 2020
  e9f22fd4
- [PowerPC] Remove UB from PPCInstrInfo when handling rotates fed by constants · e009fad3
  Nemanja Ivanovic authored Mar 18, 2020
  e009fad3