Commits · dbf910f0d95011e9485af859a10efb75bf28ee89 · Roger Ferrer / llvm-epi · GitLab

Feb 19, 2021
- [RISCV] Prevent selecting a 0 VL to X0 for the segment load/store intrinsics. · dbf910f0
  Craig Topper authored Feb 19, 2021
  dbf910f0
- [RISCV] Move SHFLI matching to DAG combine. Add 32-bit support for RV64 · 98dff5e8
  Craig Topper authored Feb 19, 2021
  98dff5e8
- [AArch64][GlobalISel] Run redundant_sext_inreg in the post-legalizer combiner · 8d3442ed
  Jessica Paquette authored Feb 17, 2021
  8d3442ed
- Make fixed-abi default for AMD HSA OS · 3c297a25
  madhur13490 authored Feb 10, 2021
  3c297a25
- [ARM] Correct vector predicate type in MVE getCmpSelInstrCost · a1c34a9d
  David Green authored Feb 19, 2021
  
  a1c34a9d
- Revert "[ARM] Expand the range of allowed post-incs in load/store optimizer" · 7a5c26e9
  David Green authored Feb 19, 2021
  7a5c26e9
- [RISCV] Address some clang-tidy warnings. NFCI. · d9531a30
  Fraser Cormack authored Feb 19, 2021
  
  d9531a30
- [AMDGPU] WQM/WWM: Fix marking of partial definitions · 8181dcd3
  Carl Ritson authored Feb 19, 2021
  8181dcd3
- [X86][AVX] getFauxShuffleMask - decode VBROADCAST(EXTRACT_VECTOR_ELT(V,0)) · 2258b367
  Simon Pilgrim authored Feb 19, 2021
  2258b367
- [X86] Fix a codegen crash in getSetCCResultType · c98644c2
  Wang, Pengfei authored Feb 19, 2021
  c98644c2
- [AArch64] Add some missing Neoverse features · 260f90bb
  Sjoerd Meijer authored Feb 18, 2021
  260f90bb
- [RISCV] Prune unneeded indexed load/store pseudo instructions. · cd4051ac
  Craig Topper authored Feb 18, 2021
  cd4051ac
- [FPEnv][AArch64] Implement lowering of llvm.set.rounding · 2c4f60e4
  Serge Pavlov authored Feb 16, 2021
  2c4f60e4
- [RISCV] Split zvlsseg searchable table into 4 separate tables. Index by... · 8ed3bbbc
  Craig Topper authored Feb 18, 2021
  8ed3bbbc
- [RISCV] Enable PrimaryKeyEarlyOut on RISCVVPseudosTable. · cf345591
  Craig Topper authored Feb 18, 2021
  cf345591
- [llvm][IR] Do not place constants with static relocations in a mergeable section · c77659e5
  Leonard Chan authored Feb 10, 2021
  c77659e5
Feb 18, 2021
- GlobalISel: Merge some AMDGPU ABI lowering code to generic code · 62d946e1
  Matt Arsenault authored Feb 07, 2021
  62d946e1
- [BasicAA] Always strip single-argument phi nodes · 70e3c9a8
  Nikita Popov authored Feb 14, 2021
  70e3c9a8
- [RISCV] Simplify VPseudoAMOEI multiclass. NFC · 0db93831
  Craig Topper authored Feb 18, 2021
  0db93831
- [AMDGPU] Correct gfx90c feature list · 5247a0d9
  Stanislav Mekhanoshin authored Feb 18, 2021
  5247a0d9
- [RISCV] Use XLenRI alias for RegInfoByHwMode instances · 74df1ffa
  Jessica Clarke authored Feb 13, 2021
  74df1ffa
- [PowerPC][AIX] Add support for vector arg passing on the stack. · bb260b1c
  Sean Fertile authored Feb 18, 2021
  bb260b1c
- [WebAssembly] Handle multiple EH_LABELs in EH pad · 6f2999b3
  Heejin Ahn authored Feb 18, 2021
  6f2999b3
- [RISCV] Add support for fixed vector MULHU/MULHS. · 156fc07e
  Craig Topper authored Feb 18, 2021
  156fc07e
- [RISCV] Add support for fixed vector sign/zero extend from mask types. · 792627be
  Craig Topper authored Feb 18, 2021
  792627be
- [RISCV] Support isel of scalable vector bitcasts · c7dd92e8
  Craig Topper authored Feb 18, 2021
  c7dd92e8
- [AArch64][SVE] Add patterns to generate FMLA/FMLS/FNMLA/FNMLS/FMAD · 8bad8a43
  Bradley Smith authored Feb 08, 2021
  8bad8a43
- [AArch64] Allow folding FMUL/FADD into FMA for FP16 types · 5b094bfe
  Bradley Smith authored Feb 12, 2021
  5b094bfe
- [RISCV] Fix typo. Use ValueType instead of LLVMType. · 065a187f
  Hsiangkai Wang authored Feb 18, 2021
  
  065a187f
- [ARM] Expand the range of allowed post-incs in load/store optimizer · 3b34b06f
  David Green authored Feb 18, 2021
  3b34b06f
- [PowerPC] Exploit the vinsw, vinsd, and vins[wd][lr]x instructions on P10 · 34dc1ccb
  Baptiste Saleil authored Feb 17, 2021
  34dc1ccb
- [RISCV] Fix bugs in pseudo instructions for masked segment load. · f1efa8ab
  Hsiangkai Wang authored Feb 18, 2021
  f1efa8ab
- [NFC][RISCV] Use concise way to describe load/store instructions. · b97d8b32
  Hsiangkai Wang authored Feb 18, 2021
  b97d8b32
- [ARM] Ensure types provided to getIntrinsicCost are valid · 33ba2206
  David Green authored Feb 18, 2021
  33ba2206
- [PowerPC] Add option for ROP Protection · b80357d4
  Stefan Pintilie authored Feb 18, 2021
  b80357d4
- [ARM] Add larger than legal ICmp costs · 1a6744e3
  David Green authored Feb 18, 2021
  1a6744e3
- [RISCV] Rewrite assert to not give unused variable warnings in Release builds · ae1e6c35
  Benjamin Kramer authored Feb 18, 2021
  ae1e6c35
- [RISCV] Begin to support more subvector inserts/extracts · d8762149
  Fraser Cormack authored Feb 17, 2021
  d8762149
- [SVE][CodeGen] Expand SVE MULH[SU] and [SU]MUL_LOHI nodes · 0176fecf
  Fraser Cormack authored Feb 17, 2021
  0176fecf
- [X86] Zero AMX config buffer for non AVX512 cases. · e9c11c19
  Wang, Pengfei authored Feb 18, 2021
  e9c11c19