Commits · ddc1b40f26b210a1650454e1ef232cf5f1b6775f · Roger Ferrer / llvm-epi · GitLab

Jul 02, 2019
- [InstCombine] reduce more checks for power-of-2-or-zero using ctpop · ddc1b40f
  Sanjay Patel authored Jul 01, 2019
  ddc1b40f
Jul 01, 2019
- [X86] Use v4i32 vzloads instead of v2i64 for vpmovzx/vpmovsx patterns where... · 3f722d40
  Craig Topper authored Jul 01, 2019
  3f722d40
- [mips] Add missing schedinfo for MIPSeh_return[32|64] instructions · fa275006
  Simon Atanasyan authored Jul 01, 2019
  fa275006
- [mips] Add virtualization ASE to P5600 scheduling definitions · 29801f78
  Simon Atanasyan authored Jul 01, 2019
  29801f78
- [mips] Add missing schedinfo for LONG_BRANCH_* instructions · 574d0a61
  Simon Atanasyan authored Jul 01, 2019
  574d0a61
- [X86] Remove several bad load folding isel patterns for VPMOVZX/VPMOVSX. · 328b2415
  Craig Topper authored Jul 01, 2019
  328b2415
- Revert [SLP] Look-ahead operand reordering heuristic. · a7972dc0
  Jordan Rupprecht authored Jul 01, 2019
  a7972dc0
- [NFC][InstCombine] More commutative tests for "shift direction in bittest" (PR42466) · 975120a2
  Roman Lebedev authored Jul 01, 2019
  975120a2
- Testing commit access through minor formatting change · 8b7a0baa
  Nilanjana Basu authored Jul 01, 2019
  8b7a0baa
- GlobalISel: Try to widen merges with other merges · c9f14f29
  Matt Arsenault authored Jul 01, 2019
  c9f14f29
- AMDGPU: Revert accidental change to test · 73dec22c
  Matt Arsenault authored Jul 01, 2019
  73dec22c
- [X86] Correct v4f32->v2i64 cvt(t)ps2(u)qq memory isel patterns · 5e7815b6
  Craig Topper authored Jul 01, 2019
  5e7815b6
- AMDGPU/GlobalISel: Handle more input argument intrinsics · bae3636f
  Matt Arsenault authored Jul 01, 2019
  bae3636f
- AMDGPU/GlobalISel: Lower kernarg segment ptr intrinsics · 9e8e8c60
  Matt Arsenault authored Jul 01, 2019
  9e8e8c60
- AMDGPU/GlobalISel: Legalize workgroup ID intrinsics · 756d8190
  Matt Arsenault authored Jul 01, 2019
  756d8190
- AMDGPU/GlobalISel: Legalize workitem ID intrinsics · e2c86cce
  Matt Arsenault authored Jul 01, 2019
  e2c86cce
- AMDGPU/GlobalISel: Custom lower control flow intrinsics · e15770ae
  Matt Arsenault authored Jul 01, 2019
  e15770ae
- AMDGPU/GlobalISel: Handle 16-bit SALU min/max · 4073b337
  Matt Arsenault authored Jul 01, 2019
  4073b337
- AMDGPU/GlobalISel: Lower SALU min/max to cmp+select · 5a7d5111
  Matt Arsenault authored Jul 01, 2019
  5a7d5111
- [X86] Avoid SFB - Fix inconsistent codegen with/without debug info(2) · e20030f6
  Robert Lougher authored Jul 01, 2019
  e20030f6
- AMDGPU/GlobalISel: Add tests for add legalization · 7f8c7209
  Matt Arsenault authored Jul 01, 2019
  7f8c7209
- AMDGPU/GlobalISel: Legalize s16 add/sub/mul · ef59cb69
  Matt Arsenault authored Jul 01, 2019
  ef59cb69
- AMDGPU/GlobalISel: Fix allowing non-boolean conditions for G_SELECT · 9470bb26
  Matt Arsenault authored Jul 01, 2019
  9470bb26
- [NFC][InstCombine] Add tests for "shift direction in bittest" (PR42466) · e6285778
  Roman Lebedev authored Jul 01, 2019
  e6285778
- GlobalISel: Verify G_MERGE_VALUES operand sizes · 03ca176a
  Matt Arsenault authored Jul 01, 2019
  03ca176a
- [GlobalISel]: Allow backends to custom legalize Intrinsics · 1023a2ec
  Aditya Nandakumar authored Jul 01, 2019
  1023a2ec
- AMDGPU/GlobalISel: RegBankSelect for sendmsg/sendmsghalt · b2ea20ee
  Matt Arsenault authored Jul 01, 2019
  b2ea20ee
- AMDGPU/GlobalISel: Legalize s16 fcmp · 40d1faf3
  Matt Arsenault authored Jul 01, 2019
  40d1faf3
- GlobalISel: Implement lower for min/max · 6f74f557
  Matt Arsenault authored Jul 01, 2019
  6f74f557
- AMDGPU/GFX10: implement ds_ordered_count changes · 10c911db
  Nicolai Haehnle authored Jul 01, 2019
  10c911db
- AMDGPU: Support GDS atomics · 4dc3b2bf
  Nicolai Haehnle authored Jul 01, 2019
  4dc3b2bf
- AMDGPU/GlobalISel: RegBankSelect for DS ordered add/swap · 1094e6a8
  Matt Arsenault authored Jul 01, 2019
  1094e6a8
- AArch64/GlobalISel: Fix trying to select invalid MIR · 732149b2
  Matt Arsenault authored Jul 01, 2019
  732149b2
- AMDGPU/GlobalISel: RegBankSelect for amdgcn.writelane · 265059ea
  Matt Arsenault authored Jul 01, 2019
  265059ea
- AMDGPU/GlobalISel: Fail instead of assert when selecting loads · a3107278
  Matt Arsenault authored Jul 01, 2019
  a3107278
- AMDGPU/GlobalISel: Complete implementation of G_GEP · 0a52e9d0
  Matt Arsenault authored Jul 01, 2019
  0a52e9d0
- AMDGPU/GlobalISel: Select G_PHI · e1006259
  Matt Arsenault authored Jul 01, 2019
  e1006259
- AMDGPU/GlobalISel: Try to select VOP3 form of add · d810ff25
  Matt Arsenault authored Jul 01, 2019
  d810ff25
- [X86] Add widenSubVector to size in bits helper. NFCI. · e3e38cce
  Simon Pilgrim authored Jul 01, 2019
  e3e38cce
- AMDGPU/GlobalISel: RegBankSelect for readlane/readfirstlane · 62d64b0c
  Matt Arsenault authored Jul 01, 2019
  62d64b0c