Commits · e2d68c2fa47c260e1a640a2d2595a7f6d6fe5a48 · Roger Ferrer / llvm-epi · GitLab

Apr 14, 2023
- [AArch64] Combine SELECT_CC patterns that match smin(a,0) and smax(a,0) · 88b80760
  Cameron McInally authored Apr 14, 2023
  88b80760
- [AArch64] Teach the AArch64 backend patterns to generate the RAX1 instruction. · b4c1b07d
  Shreyansh Chouhan authored Apr 14, 2023
  b4c1b07d
- [X86] combineSetCCMOVMSK - fold anyof/noneof movmskps/movmskpd -> testps/testpd · 3a0c1d5a
  Simon Pilgrim authored Apr 14, 2023
  3a0c1d5a
- [AMDGPU] Less aggressively break large PHIs · b3b3cb2d
  pvanhout authored Apr 07, 2023
  b3b3cb2d
- [X86] SimplifyDemandedBitsForTargetNode - improve TESTPS/TESTPD handling for duplicated operands · 6523e2f4
  Simon Pilgrim authored Apr 14, 2023
  6523e2f4
- [llvm-c] Remove PassRegistry and initialization APIs · 62ef97e0
  Nikita Popov authored Mar 01, 2023
  62ef97e0
- [PowerPC] Update `incr` after resetting the register in MI · eee024bf
  Kai Luo authored Apr 14, 2023
  eee024bf
- [AMDGPU] Add backend support for new PAL ELF Metadata 3.0 · fc83f1de
  David Stuttard authored Feb 20, 2023
  fc83f1de
- [AMDGPU] Don't S_MOV_B32 into $scc · b9ba0536
  Diana Picus authored Apr 12, 2023
  b9ba0536
- [RISCV] Support vector strict_fsetcc/fsetccs. · d83620d1
  Yeting Kuo authored Apr 10, 2023
  d83620d1
Apr 13, 2023
- [AArch64] Fix -Wunused-variable in -DLLVM_ENABLE_ASSERTIONS=off builds · ea31a17d
  Fangrui Song authored Apr 13, 2023
  
  ea31a17d
- [X86] Only fold PTEST->TESTP on AVX targets · 7ea34403
  Simon Pilgrim authored Apr 13, 2023
  7ea34403
- [CostModel][X86] Add latency/code-size/size-latency target costs for minnum/maxnum intrinsics · 48fca4b6
  Simon Pilgrim authored Apr 13, 2023
  48fca4b6
- [AMDGPU] Allow use of TTMP registers in AMDGPUResourceUsageAnalysis · 2d39f5b5
  Jay Foad authored Apr 13, 2023
  2d39f5b5
- [AMDGPU] Avoid else-after-return in isLegalAddressingMode. NFC. · cf736e23
  Jay Foad authored Apr 13, 2023
  
  cf736e23
- [AArch64] Add more efficient vector bitcast for AArch64 · 3653722c
  Lawrence Benson authored Apr 13, 2023
  3653722c
- [ARM] Fix Crashes in fp16/bf16 Inline Asm · 9ee4fe63
  Archibald Elliott authored Apr 13, 2023
  9ee4fe63
- [AArch64][GISel] Legalize non-power-of-two G_CTTZ · 41eba6cd
  Archibald Elliott authored Apr 05, 2023
  41eba6cd
- [TTI][X86] getMinMaxCost - use existing float minnum/maxnum intrinsic cost... · 2bfd7a07
  Simon Pilgrim authored Apr 13, 2023
  2bfd7a07
- [TTI] getExtendedReductionCost - replace std::optional<FastMathFlags> args with FastMathFlags · fb8038db
  Simon Pilgrim authored Apr 13, 2023
  fb8038db
- [WebAssembly] `AsmTypeCheck` support to br instr · db1dac1e
  Congcong Cai authored Apr 13, 2023
  db1dac1e
- [TTI] getMinMaxReductionCost - add FastMathFlag argument · 9e30b87a
  Simon Pilgrim authored Apr 13, 2023
  9e30b87a
- [AArch64][CodeGen] Use interleave store for streaming compatible functions · c8192670
  Caroline Concatto authored Apr 13, 2023
  c8192670
- [AMDGPU] Remove CC exception for Promote Alloca Limits · fd1d6087
  pvanhout authored Apr 12, 2023
  fd1d6087
- [WebAssembly] Handle DebugLoc in DebugValueManager · d20a1b87
  Heejin Ahn authored Mar 26, 2023
  d20a1b87
- [NFC][m68k] Remove the lingering codebeads-related part in M68kInstrFormats.td · 1290d0dd
  Sheng authored Apr 08, 2023
  
  1290d0dd
- [RISCV][TTI] Call improveShuffleKindFromMask like all the other backends · b0e0c1e4
  Philip Reames authored Apr 12, 2023
  b0e0c1e4
- [X86 isel] Remove lane requirement from lowerShuffleAsUNPCKAndPermute · ef38880c
  Han Zhu authored Feb 13, 2023
  ef38880c
Apr 12, 2023
- [CodeGen][RISCV] Change Shadow Call Stack Register to X3 · aa1d2693
  Paul Kirth authored Mar 20, 2023
  aa1d2693
- [RISCV] Support llvm.lround intrinsics with i32 return type on RV64. · d7c97e91
  Craig Topper authored Apr 12, 2023
  d7c97e91
- Revert "Move DBG_VALUE's that depend on loads to after a" · 9bc5e8c8
  Shubham Sandeep Rastogi authored Apr 12, 2023
  9bc5e8c8
- Move DBG_VALUE's that depend on loads to after a · 0aaf6341
  Shubham Sandeep Rastogi authored Feb 07, 2023
  0aaf6341
- [AArch64][SVE] Extend predicated fadd/fsub patterns to negative zero · 9af92455
  David Green authored Apr 12, 2023
  9af92455
- [AArch64][GISel] Legalize non-power-of-two G_CTLZ · 56065f8f
  Archibald Elliott authored Apr 05, 2023
  56065f8f
- [AArch64][SVE] Extend predicated fma patterns to negative zero · cfee494f
  David Green authored Apr 12, 2023
  cfee494f
- [TTI][X86] getMinMaxCost - use existing integer min/max intrinsic cost values... · 63c38953
  Simon Pilgrim authored Apr 12, 2023
  63c38953
- [X86] combinePTESTCC - attempt to use TESTPS/TESTPD instead of... · d5143827
  Simon Pilgrim authored Apr 12, 2023
  d5143827
- [X86] Cleanup reduction cost table names. NFC. · 4b5a4d48
  Simon Pilgrim authored Apr 12, 2023
  4b5a4d48
- [X86] SimplifyDemandedBitsForTargetNode - add TESTPS/TESTPD support · 1e155ce9
  Simon Pilgrim authored Apr 12, 2023
  1e155ce9
- AMDGPU: Push fneg into bitcast of integer select · f608ac62
  Matt Arsenault authored Jan 26, 2023
  f608ac62