Commits · e50b141a13dcfb8938422484d3719d18416ba5ca · Roger Ferrer / llvm-epi · GitLab

Jun 21, 2022
- [RISCV] Remove true_mask patterns for VRGATHER. · e50b141a
  Craig Topper authored Jun 21, 2022
  e50b141a
- [AArch64] Move add_and_or_is_add pattern. NFC · 939c5709
  David Green authored Jun 21, 2022
  939c5709
- [SystemZ] Fix the cost function for vector zero extend. · bfca9a0b
  Jonas Paulsson authored Aug 31, 2020
  bfca9a0b
- [X86] fold (and (mul x, c1), c2) -> (mul x, (and c1, c2)) iff c2 is all/no bits mask · ac4cb177
  Simon Pilgrim authored Jun 21, 2022
  ac4cb177
- [AMDGPU] Update SPI_SHADER_PGM_RSRC2_PS.EXTRA_LDS_SIZE for GFX11 · 929a8ad2
  Jay Foad authored Apr 06, 2022
  929a8ad2
- [X86] combineAndnp - constant fold ANDNP(C,X) -> AND(~C,X) · 057db200
  Simon Pilgrim authored Jun 21, 2022
  057db200
- [AArch64] Remove unnecessary funnel shift sve costs. · fb4d3d23
  David Green authored Jun 21, 2022
  fb4d3d23
- [X86] computeKnownBitsForTargetNode - add X86ISD::VBROADCAST_LOAD handling · 843d43e6
  Simon Pilgrim authored Jun 21, 2022
  843d43e6
- [AArch64] Add Extract(DUP(C)) as a canonical constant. · 3f818414
  David Green authored Jun 21, 2022
  3f818414
- [AMDGPU] Set GFX11 null export target based on export attributes · 62abc8c2
  Carl Ritson authored Jul 28, 2021
  62abc8c2
- [llvm] Don't use Optional::getValue (NFC) · 7a47ee51
  Kazu Hirata authored Jun 20, 2022
  
  7a47ee51
- [PowerPC][ctrloop] handles calls in preheader before MTCTRloop · 9cfbe7bb
  Chen Zheng authored Jun 21, 2022
  
  9cfbe7bb
- [RISCV] Add RISCVISD opcode for PseudoAddTPRel. · e01353f8
  Craig Topper authored Jun 20, 2022
  e01353f8
- Recommit "[RISCV] Enable subregister liveness tracking for RVV." · 59cde213
  Craig Topper authored Jun 20, 2022
  59cde213
- [AARCH64 folding] Do not fold any copy with NZCV · 163c77b2
  Serguei Katkov authored Jun 08, 2022
  163c77b2
- Don't use Optional::hasValue (NFC) · d66cbc56
  Kazu Hirata authored Jun 20, 2022
  
  d66cbc56
- Don't use Optional::hasValue (NFC) · 0916d96d
  Kazu Hirata authored Jun 20, 2022
  
  0916d96d
- Don't use Optional::hasValue (NFC) · 064a08cd
  Kazu Hirata authored Jun 20, 2022
  
  064a08cd
- [PowerPC] add a new pass to expand ctr loop pseudos · a71fe49b
  Chen Zheng authored Apr 08, 2022
  a71fe49b
- [RISCV] Add merge operand to RISCVISD::VRGATHER*_VL nodes. · 16d3a82d
  Craig Topper authored Jun 20, 2022
  16d3a82d
- [X86] Make sure SF is updated when optimizing for `jg/jge/jl/jle` · edcc68e8
  Phoebe Wang authored Jun 21, 2022
  edcc68e8
Jun 20, 2022
- [AMDGPU] Mark GFX11 dual source blend export as strict-wqm · 732eed40
  Ruiling Song authored Mar 09, 2022
  732eed40
- [AMDGPU] Tag GFX11 LDS loads as using strict_wqm · 29621c13
  Piotr Sobczak authored Mar 11, 2021
  29621c13
- [AMDGPU] Add support for GFX11 LDSDIR hazards · 13107c27
  Jay Foad authored Jun 16, 2022
  13107c27
- [RISCV] Fix crash when costing scalable gather/scatter of pointer · 0aebd1d8
  Philip Reames authored Jun 20, 2022
  0aebd1d8
- [PowerPC] Disable automatic generation of STXVP · e09f6ff3
  Nemanja Ivanovic authored Jun 20, 2022
  e09f6ff3
- Don't use Optional::hasValue (NFC) · ad7ce1e7
  Kazu Hirata authored Jun 20, 2022
  
  ad7ce1e7
- Don't use Optional::hasValue (NFC) · 5413bf1b
  Kazu Hirata authored Jun 20, 2022
  
  5413bf1b
- [AArch64] Known bits for AArch64ISD::DUP · c0ecbfa4
  David Green authored Jun 20, 2022
  c0ecbfa4
- [X86] LowerINSERT_VECTOR_ELT - always lower v32i8/v16i16 allones insertions on AVX1 as OR ops · 82549660
  Simon Pilgrim authored Jun 20, 2022
  82549660
- [BasicTTI] Allow generic handling of scalable vector fshr/fshl · db85345f
  Philip Reames authored Jun 20, 2022
  db85345f
- [llvm] Don't use Optional::hasValue (NFC) · e0e687a6
  Kazu Hirata authored Jun 20, 2022
  
  e0e687a6
- [RISCV] Delete unexercised VL=0 vsetvli compatibility logic · 14847098
  Philip Reames authored Jun 20, 2022
  14847098
- [NFC] Simplify code · d154d0ac
  Guillaume Chatelet authored Jun 20, 2022
  
  d154d0ac
- [RISCV] Fold prepass back into InsertVSETVLI data flow [nfc-ish] · dc562d57
  Philip Reames authored Jun 20, 2022
  dc562d57
- [RISCV] Assert initial load/store SEW is the EEW · 820e84e0
  Philip Reames authored Jun 20, 2022
  820e84e0
- [AMDGPU] Reorder cases. NFC. · ba306216
  Jay Foad authored Jun 20, 2022
  
  ba306216
- [AArch64][SME] Add the zero intrinsic · 01335863
  David Sherwood authored Jun 14, 2022
  01335863
- [AMDGPU] Increase instruction cache line size to 128 bytes for GFX11 · d7762a3b
  Jay Foad authored Mar 10, 2021
  d7762a3b
- [AMDGPU] Remove a duplicate atomic fadd pattern · b8e32e80
  Jay Foad authored Jun 20, 2022
  b8e32e80