Commits · e8b55cf7b70a695d158d3e172d1124e36d81a8fc · Roger Ferrer / llvm-epi · GitLab

Nov 17, 2021
- [SCEV] Apply loop guards when computing max BTC for arbitrary steps. · e8b55cf7
  Florian Hahn authored Nov 17, 2021
  e8b55cf7
- [RISCV] Add extra -early-live-intervals test coverage · 4be705d6
  Jay Foad authored Oct 08, 2021
  4be705d6
- [NFC][X86][Costmodel] Improve test coverage for i32->i64 vector *ext · 496ccb54
  Roman Lebedev authored Nov 17, 2021
  
  496ccb54
- [X86][Costmodel] `*ext v64i1 to v32i16` can appear after legalization, cost is... · 2037ec72
  Roman Lebedev authored Nov 17, 2021
  2037ec72
- [X86][Costmodel] `trunc v32i16 to v64i1` can appear after legalization, cost... · 23b194bf
  Roman Lebedev authored Nov 17, 2021
  23b194bf
- [SelectionDAG] Make WidenVecRes_SELECT work for scalable vectors · f7eb061a
  Eric Tang authored Nov 16, 2021
  f7eb061a
Nov 16, 2021
- [ARM] Update test comments after D114018. NFC · 4e37e325
  David Green authored Nov 16, 2021
  4e37e325
- Limit test to x86 for now. · b75cc51d
  Leonard Chan authored Nov 16, 2021
  
  b75cc51d
- [llvm-objcopy] Add --update-section · 25bcd942
  Leonard Chan authored Oct 20, 2021
  25bcd942
- [X86] Add shift by splat modulo amount vector tests · aeb3c772
  Simon Pilgrim authored Nov 16, 2021
  aeb3c772
- [SCEV] Canonicalize X - urem X, Y patterns · 8d85e945
  Philip Reames authored Nov 16, 2021
  8d85e945
- [Loads] Handle addrspacecast constant expressions when determining dereferenceability · c95a9f46
  Arthur Eubanks authored Nov 16, 2021
  c95a9f46
- [PowerPC] PPC backend optimization on conditional trap intrustions · ae27ca9a
  Victor Huang authored Nov 16, 2021
  ae27ca9a
- [test] Precommit test for D114015 · 877d6e9b
  Arthur Eubanks authored Nov 16, 2021
  
  877d6e9b
- [tests] Add coverage for different forms of X - urem X, Y · 3dd6d5b6
  Philip Reames authored Nov 16, 2021
  
  3dd6d5b6
- autogen a SCEV test file · 56ae2cfe
  Philip Reames authored Nov 16, 2021
  
  56ae2cfe
- [AArch64] Fix TypeSize->uint64_t implicit conversion in AArch64ISelLowering::hasAndNot · 46074590
  David Sherwood authored Nov 16, 2021
  46074590
- [amdgpu] Don't crash on empty global ctor/dtor · 30b29db7
  Jon Chesterfield authored Nov 16, 2021
  30b29db7
- [InstCombine] canonicalize icmp with trunc op into mask and cmp, part 2 · 8fce94f9
  Sanjay Patel authored Nov 16, 2021
  8fce94f9
- [SLP]Improve cost of the gather nodes. · 900cc1a2
  Alexey Bataev authored Nov 12, 2021
  900cc1a2
- [AIX] XFAIL lto-comp-dir.ll for lack of .file directive support · 2f43a656
  Jake Egan authored Nov 16, 2021
  2f43a656
- [SLP][NFC]Add more tests for shuffles that can be optimized after SLP, · 51c0b684
  Alexey Bataev authored Nov 16, 2021
  51c0b684
- [IndVarSimplify] Reduce nondeterministic behaviour in visitIVCast. · 305816ff
  Sander.DeSmalen@arm.com authored Nov 16, 2021
  305816ff
- [llvm-reduce] Allow writing temporary files as bitcode. · 28d95a26
  Florian Hahn authored Nov 16, 2021
  28d95a26
- [SCEV] Support rewriting ZExt expressions with loop guard info. · b7aec4f0
  Florian Hahn authored Nov 16, 2021
  b7aec4f0
- [AArch64][SVE] Instcombine SVE LD1/ST1 to stock LLVM IR · f526c600
  Matt Devereau authored Nov 04, 2021
  f526c600
- [ARM] Add datalayout to costmodel tests. NFC · 309f1e4a
  David Green authored Nov 16, 2021
  309f1e4a
- [CGP][PowerPC] Pre-commit test case for D113872. NFC. · c0da8a4e
  Kai Luo authored Nov 16, 2021
  
  c0da8a4e
- [STATEPOINT] Force implicit-def for lr register. · 0ecb12a2
  Serguei Katkov authored Oct 05, 2021
  0ecb12a2
- [GlobalISel] Add a store-merging optimization pass and enable for AArch64. · dc84770d
  Amara Emerson authored Nov 15, 2021
  dc84770d
- [llvm-profgen] Add switch to allow use of first loadable segment for calculating offset · f7976edc
  Wenlei He authored Nov 11, 2021
  f7976edc
- [RISCV] Override TargetLowering::hasAndNot for Zbb. · 391b0ba6
  Craig Topper authored Nov 15, 2021
  391b0ba6
- [RISCV] Add test cases to prepare for overring TargetLowering::hasAndNot. NFC · d90eeab0
  Craig Topper authored Nov 15, 2021
  d90eeab0
- [X86] Fix crash with inline asm using wrong register name · b484fa82
  Fabian Wolff authored Nov 16, 2021
  b484fa82
- AMDGPU: Mark prolog/epilog SCC defs as dead · 659887b4
  Matt Arsenault authored Nov 13, 2021
  659887b4
- AMDGPU: Regenerate test checks · e6bfbd7e
  Matt Arsenault authored Nov 13, 2021
  
  e6bfbd7e
- [DAGCombiner] Prevent unfoldMaskedMerge from creating an AND with two inverted inputs. · 233def40
  Craig Topper authored Nov 15, 2021
  233def40
- [InstSimplify] Fold A|B | (A^B) --> A|B · 62c51a72
  Mehrnoosh Heidarpour authored Nov 15, 2021
  62c51a72
- [RISCV] Optimize immediate materialisation with SH*ADD · 4c3d916c
  Ben Shi authored Nov 11, 2021
  4c3d916c
- [RISCV][test] Add more tests of immediate materialisation · 39256ed5
  Ben Shi authored Nov 10, 2021
  39256ed5