Commits · ee95fe5caa3c32a1a9de6c487bbbc78af837af61 · Roger Ferrer / llvm-epi · GitLab

Feb 28, 2022
- [RISCV] Optimize (sext.w, srli) to sraiw with Zba. · 7f811ce1
  Chenbing Zheng authored Feb 28, 2022
  7f811ce1
Feb 27, 2022
- [SDAG] fold (rotate X) eq/ne (0/-1) · 69684b84
  Sanjay Patel authored Feb 27, 2022
  69684b84
- [x86] add tests for setcc eq/ne 0/-1 of rotate; NFC · 35de5125
  Sanjay Patel authored Feb 27, 2022
  35de5125
- [X86][SSE] Attempt to lower vec_reduce_add patterns with PSADBW for zero-extended vXi8 sources · 2b46417a
  Simon Pilgrim authored Feb 27, 2022
  2b46417a
- [SDAG] fold bitwise logic with shifted operands · acb96ffd
  Sanjay Patel authored Feb 27, 2022
  acb96ffd
- [DAG] Ensure type is legal for bswap(shl(x,c)) -> zext(bswap(trunc(shl(x,c-bw/2)))) fold · fadd20f8
  Simon Pilgrim authored Feb 27, 2022
  fadd20f8
Feb 25, 2022
- [BPF] Fix tests that fail if /tmp/t.c exists · f58fb8ae
  Reid Kleckner authored Feb 25, 2022
  f58fb8ae
- [Mangler] Mangle aliases to fastcall/vectorcall functions correctly · 54b909de
  Amanieu d'Antras authored Feb 25, 2022
  54b909de
- [RISCV] Remove tab character from test. Autogenerate CHECK lines. NFC · 5e33bd80
  Craig Topper authored Feb 25, 2022
  5e33bd80
- [AMDGPU][NFC]: Emit metadata for hidden_heap_v1 kernarg · ca62b1db
  Changpeng Fang authored Feb 25, 2022
  ca62b1db
- [AArch64] Add tests for tbl + cmp splitting. · c679fbee
  Florian Hahn authored Feb 25, 2022
  c679fbee
- [Sample-PGO] Emit FS discriminators only when -fdebug-info-for-profiling is set · ccbbb4f6
  Rong Xu authored Feb 25, 2022
  ccbbb4f6
- [SVE] Add missing splat patterns for bfloat vectors. · 16ee1029
  Paul Walker authored Feb 24, 2022
  16ee1029
- [SVE] Refactor complex immediate pattern used by CPY/DUP. · 7ab78f34
  Paul Walker authored Feb 23, 2022
  7ab78f34
- [AArch64] Add test cases where zext can be lowered to series of tbl. · 166968a8
  Florian Hahn authored Feb 25, 2022
  166968a8
- [WebAssembly] Covert llvm/test/MC/WebAssembly/reloc-code.ll to asm. NFC · db7b1af8
  Sam Clegg authored Feb 24, 2022
  db7b1af8
- [X86] Regenerate x86-cmov-converter.ll checks · edaf7187
  Simon Pilgrim authored Feb 25, 2022
  
  edaf7187
- [X86] Combine ADC(ADD(X,Y),0,Carry) -> ADC(X,Y,Carry) · eb1ff70f
  Pawe Bylica authored Feb 25, 2022
  eb1ff70f
- [RISCV] Fix a mistake in PostprocessISelDAG · 865fe131
  Haocong.Lu authored Feb 25, 2022
  865fe131
- Revert rG87753cebf5f861eee418d6bce155dfa0b00f9878 "[X86]... · 748bf545
  Simon Pilgrim authored Feb 25, 2022
  748bf545
- [NVPTX][AsmPrinter] Emit .attribute(.managed) for global variable declarations · 3fe6f938
  Kristina Bessonova authored Feb 25, 2022
  3fe6f938
- [SCEV] Don't try to reuse expressions with offset · d9715a72
  Nikita Popov authored Feb 22, 2022
  d9715a72
- [SystemZ] [z/OS] Add support for generating huge (1 MiB) stack frames in XPLINK64 · eb3e09c9
  Neumann Hon authored Feb 25, 2022
  eb3e09c9
- [RISCV] DAG Combine vcpop and vfirst with VL=0 to li imm · b20e80aa
  Chenbing Zheng authored Feb 25, 2022
  b20e80aa
- [RISCV] Update computeTargetABI from llc as well as clang · 4e115b7d
  Zakk Chen authored Feb 24, 2022
  4e115b7d
- [AMDGPU] Extend pre-emit peephole to redundantly masked VCC · 565af157
  Carl Ritson authored Feb 25, 2022
  565af157
Feb 24, 2022
- Revert "Encode address offsets of basic blocks relative to the end of the previous basic blocks." · aeec9671
  Rahman Lavaee authored Feb 24, 2022
  aeec9671
- [AArch64][x86] add tests for bitwise logic + shifts; NFC · ecf606cb
  Sanjay Patel authored Feb 24, 2022
  
  ecf606cb
- [RISCV] Add tests for (neg (abs X)) where the abs has an additional user. · 6159f059
  Craig Topper authored Feb 24, 2022
  
  6159f059
- [AMDGPU] Divergence-driven instruction selection for bitreverse · 05d79e35
  Jay Foad authored Feb 14, 2022
  05d79e35
- [DAG] Attempt to fold bswap(shl(x,c)) -> zext(bswap(trunc(shl(x,c-bw/2)))) · 370ebc9d
  Simon Pilgrim authored Feb 24, 2022
  370ebc9d
- [AArch64] Regenerate dp1.ll test, NFC · b3e9fdd1
  David Green authored Feb 24, 2022
  b3e9fdd1
- [AMDGPU] Extend SILoadStoreOptimizer to handle global stores · 3279e440
  Stanislav Mekhanoshin authored Feb 22, 2022
  3279e440
- [AArch64] Async unwind - Always place the first LDP at the end when ReverseCSRRestoreSeq is true · 17e85cd4
  Momchil Velikov authored Feb 24, 2022
  17e85cd4
- [AMDGPU] Fix combined MMO in load-store merge · cefa1c5c
  Stanislav Mekhanoshin authored Feb 22, 2022
  cefa1c5c
- [X86] Introduce x86-cmov-converter-force-all · e38fc14c
  Amir Ayupov authored Feb 15, 2022
  e38fc14c
- [RISCV] Add Zbb RUN lines to neg-abs.ll. · 2aa1c6fc
  Craig Topper authored Feb 24, 2022
  
  2aa1c6fc
- [AArch64] Async unwind - helper functions to decide on CFI emission · 25e92920
  Momchil Velikov authored Feb 24, 2022
  25e92920
- [RISCV] Update some tests to use floating point ABI where it makes sense. · f69078b7
  Craig Topper authored Feb 24, 2022
  f69078b7
- [AArch64] Async unwind - do not schedule frame setup/destroy · fd7e59f0
  Momchil Velikov authored Feb 24, 2022
  fd7e59f0