Commits · f204229e4573a7a5bb2fcef747a012f306637818 · Roger Ferrer / llvm-epi · GitLab

Oct 08, 2022
- [X86] Remove AVX512VP2INTERSECT from Sapphire Rapids. · 566c277c
  Freddy Ye authored Oct 08, 2022
  566c277c
- [LoongArch] Do not assert value type in isFPImmLegal · f4ccb577
  gonglingqin authored Oct 08, 2022
  f4ccb577
- [RISCV] Fix incorrect parenthese placement in comment. NFC · f749b2d9
  Craig Topper authored Oct 07, 2022
  
  f749b2d9
- [VP][RISCV] Add vp.smax/smin/umax/umin intrinsics · 9f67047c
  Craig Topper authored Oct 07, 2022
  9f67047c
- [Hexagon] Implement helper to get intrinsic for instruction opcode · 09d84e0a
  Krzysztof Parzyszek authored Oct 07, 2022
  09d84e0a
- [GlobalISel] Mark mi_match as nodiscard · 42cb2f8b
  Jessica Paquette authored Oct 07, 2022
  42cb2f8b
Oct 07, 2022
- Add support for CUDA-11.8 and sm_{87,89,90} GPUs. · 9a01cca6
  Artem Belevich authored Aug 09, 2022
  9a01cca6
- AMDGPU: Update SlotIndexes independently of LiveIntervals · 74ef03d3
  Matt Arsenault authored Sep 15, 2022
  74ef03d3
- [Hexagon] Formatting changes, NFC · d184045d
  Krzysztof Parzyszek authored Oct 06, 2022
  
  d184045d
- [Hexagon] Add couple of helper functions in HexagonVectorCombine · e492cdc3
  Krzysztof Parzyszek authored Oct 06, 2022
  e492cdc3
- [Hexagon] Add default parameter to HexagonVectorCombine::getIntTy, NFC · 06019b8e
  Krzysztof Parzyszek authored Oct 06, 2022
  
  06019b8e
- [Hexagon] Make HexagonSubtarget::isHVXVectorType take EVT instead of MVT · d376b266
  Krzysztof Parzyszek authored Oct 06, 2022
  d376b266
- [AMDGPU] Fix a warning · 7f90597b
  Kazu Hirata authored Oct 07, 2022
  7f90597b
- [Hexagon] Replace llvm::Optional with std::optional, NFC · 2216d8f6
  Krzysztof Parzyszek authored Sep 28, 2022
  
  2216d8f6
- [Hexagon] Constify member refererence, NFC · 473210ae
  Krzysztof Parzyszek authored Sep 27, 2022
  
  473210ae
- [AMDGPU][MC][GFX11] Correct v_fmac_.*_e64_dpp · 8f8e4e3b
  Dmitry Preobrazhensky authored Oct 07, 2022
  8f8e4e3b
- [AMDGPU][GFX11][NFC] Refactor VOPD handling in codegen · 1d1c7555
  Dmitry Preobrazhensky authored Oct 07, 2022
  1d1c7555
- [AMDGPU][MC][GFX11] Add VOPD VGPR bank access validation · fd7b0eea
  Dmitry Preobrazhensky authored Oct 07, 2022
  fd7b0eea
- [AArch64] Lower multiplication by a constant int to madd · 75358f06
  zhongyunde authored Oct 07, 2022
  75358f06
- [VP][RISCV] Add vp.roundtozero and its RISC-V support · dbc681c9
  eopXD authored Oct 04, 2022
  dbc681c9
- [DirectX backend] Add analysis to collect DXILResources · 22018555
  Xiang Li authored Oct 04, 2022
  22018555
- [RISCV] Use mask agnostic policy for isel patterns where the merge operand is IMPLICIT_DEF. · 3b20765c
  Craig Topper authored Oct 06, 2022
  3b20765c
- [RISCV] Use branchless form for selects with -1 in either arm · 79f0413e
  Philip Reames authored Oct 06, 2022
  79f0413e
- [RISCV] Verify that policy operands only exist on instructions with tied passthru operands · 02751655
  Philip Reames authored Oct 06, 2022
  02751655
Oct 06, 2022
- [DAG] Extract helper for (neg x) [nfc] · 04bb32e5
  Philip Reames authored Oct 06, 2022
  04bb32e5
- [X86] Do not emit JCC to __x86_indirect_thunk · eac3e5c3
  Joao Moreira authored Oct 04, 2022
  eac3e5c3
- [RISCV] Optimization for using compressed beqz and bnez PR#56391 · 0e6c1576
  Ivan Tetyushkin authored Oct 06, 2022
  0e6c1576
- [RISCV][InsertVSETVLI] Default to MA not MU · d89d45ca
  Philip Reames authored Oct 06, 2022
  d89d45ca
- [RISCV][InsertVSETVLI] Treat mask policy as undemanded if usesMaskPolicy is false · afb45ffc
  Philip Reames authored Oct 06, 2022
  afb45ffc
- [AA] Remove unused template argument from AAResultBase (NFC) · 3d0b5f01
  Nikita Popov authored Sep 27, 2022
  3d0b5f01
- [AMDGPU][GISel] Add missing V2S16 BUILD_VECTOR_TRUNC legalization · bb71079e
  Pierre van Houtryve authored Oct 04, 2022
  bb71079e
- [SPIRV] read kernel arg attributes from fuction/module metadata · 25ee36c6
  Ilia Diachkov authored Oct 04, 2022
  25ee36c6
- [AArch64][KCFI] Define Size for KCFI_CHECK · 43f4c215
  Sami Tolvanen authored Oct 05, 2022
  43f4c215
Oct 05, 2022
- [RISCV][ISel] Finally fix the UBSan error · 6e440ee2
  Quentin Colombet authored Oct 05, 2022
  6e440ee2
- [RISCV][ISel] Attempt to fix UBSan error · 6bbe7d37
  Quentin Colombet authored Oct 05, 2022
  6bbe7d37
- [RISCV][ISel] Fold extensions when all the users can consume them · c5c2de28
  Quentin Colombet authored Oct 03, 2022
  c5c2de28
- [AArch64] Add tablegen patterns for bf16 trn/zip/uzp. · 03b14548
  David Green authored Oct 05, 2022
  03b14548
- [RISCV][ISel] Refactor the formation of VW operations · 4852f26a
  Quentin Colombet authored Sep 22, 2022
  4852f26a
- [AMDGPU] Fix V_CMP_CLASS_F16_t16_e64 src1 type. · 203d0b0e
  Joe Nash authored Sep 29, 2022
  203d0b0e
- [RISCV][CodeGen] Add Scheduling for vset{i}vl{i} instruction · fbf8aa1b
  Michael Maitland authored Oct 04, 2022
  fbf8aa1b