Commits · f6ae50f710d02d8553d28192a1f048b2a9e1fc4d · Roger Ferrer / llvm-epi · GitLab

Nov 14, 2023
- [SLP]Emit actual bitwidth for analyzed MinBitwidth nodes, NFCI. · f6ae50f7
  Alexey Bataev authored Oct 23, 2023
  f6ae50f7
- [SelectionDAG] Handling Oversized Alloca Types under 32 bit Mode to Avoid Code... · c8b11091
  Qiongsi Wu authored Nov 14, 2023
  c8b11091
- [CFIFixup] Allow function prologues to span more than one basic block (#68984) · 33374c44
  Momchil Velikov authored Nov 14, 2023
  33374c44
- [InstCombine] Fold xored one-complemented operand comparisons (#69882) · daddf402
  elhewaty authored Nov 14, 2023
  daddf402
- [CodeGen][AArch64] Set min jump table entries to 13 for AArch64 targets (#71166) · bdc0afc8
  David Sherwood authored Nov 14, 2023
  bdc0afc8
- [DAG] foldABSToABD - support abs(*ext(x) - *ext(y)) -> zext(abd*(x, y)) from... · 074e4ae0
  Simon Pilgrim authored Nov 14, 2023
  074e4ae0
- [X86] Regenerate expand-vp-int-intrinsics.ll · 66845418
  Simon Pilgrim authored Nov 14, 2023
  66845418
- [AMDGPU] Use immediates for stack accesses in chain funcs (#71913) · eb3c02fd
  Diana authored Nov 14, 2023
  eb3c02fd
- [AArch64][SME2] Add ldr_zt, str_zt builtins and intrinsics (#71795) · cc124498
  Matthew Devereau authored Nov 14, 2023
  cc124498
- [CFIFixup] Precommit test ahead of multi-block prologues support (#72033) · 65eaec82
  Momchil Velikov authored Nov 14, 2023
  65eaec82
- [IR] Remove support for lshr/ashr constant expressions (#71955) · 56c1d301
  Nikita Popov authored Nov 14, 2023
  56c1d301
- [FileCheck] Avoid capturing group for {{regex}} (#72136) · a3eeef82
  Nikita Popov authored Nov 14, 2023
  a3eeef82
- [CGP] Drop nneg flag when moving zext past instruction (#72103) · c9832da3
  Nikita Popov authored Nov 14, 2023
  c9832da3
- Reenable note-amd-valid-v2.test on big endian · 4574fe97
  pvanhout authored Nov 14, 2023
  
  4574fe97
- [PowerPC] Precommit test to show impact of early-ifcvt on target without `isel`. NFC. · acdf7c8f
  Kai Luo authored Nov 14, 2023
  
  acdf7c8f
- [InstCombine] When -A + B both have nsw flag, set nsw flag. (#72127) · 3c037b73
  Z572 authored Nov 14, 2023
  3c037b73
- [RISCV][GISel] Support G_UMIN/UMAX/SMIN/SMAX legal with Zbb. (#72182) · 028ed612
  Craig Topper authored Nov 13, 2023
  
  028ed612
- [SCCP] Infer nneg on existing zext (#72143) · ed964304
  Yingwei Zheng authored Nov 14, 2023
  ed964304
- ValueTracking: Handle compare gt to -inf in class identification (#72086) · 0e1a52f5
  Matt Arsenault authored Nov 14, 2023
  0e1a52f5
- [DebugInfo] Move jump table test to X86 directory (#72118) · 45a92acf
  HaohaiWen authored Nov 14, 2023
  45a92acf
- [RISCV] Add tests for selecting G_BRCOND+G_ICMP. NFC · 0a459dd4
  Craig Topper authored Nov 13, 2023
  0a459dd4
Nov 13, 2023
- [RISCV][GISel] Update legalize-smin.mir and legalize-smax.mir to test G_SMIN/G_SMAX. · 29d75cb9
  Craig Topper authored Nov 13, 2023
  29d75cb9
- Hexagon: add support for system instructions (#72063) · bd91cf8d
  androm3da authored Nov 13, 2023
  bd91cf8d
- [RISCV] Select zext as sext when sign bit is 0 for -riscv-experimental-rv64-legal-i32 · 915e0924
  Craig Topper authored Nov 13, 2023
  915e0924
- [RISCV][GISel] Add really basic support for FP regbank selection for G_LOAD/G_STORE. (#70896) · 05300222
  Craig Topper authored Nov 13, 2023
  05300222
- [RISCV] Legalize G_CTLZ/G_CTLZ_ZERO_UNDEF/G_CTTZ/G_CTTZ_ZERO_UNDEF. (#72014) · 70ce047f
  Craig Topper authored Nov 13, 2023
  70ce047f
- [LAA] Refine tests added in 9c535a3c . · c491c933
  Florian Hahn authored Nov 13, 2023
  c491c933
- [X86] Simplify regex in pr42616.ll test (#71980) · 877226f0
  Tom Stellard authored Nov 13, 2023
  
  877226f0
- [DebugInfo] Implement TAG_label entries for debug_names (#71724) · a195d1fc
  Felipe de Azevedo Piovezan authored Nov 13, 2023
  a195d1fc
- [RISCV][GISel] Update RV64 legalize-ctpop.mir to account for constant shift amounts being i64 now. · d8576e45
  Craig Topper authored Nov 13, 2023
  d8576e45
- [RISCV][GISel] Legalize G_CTPOP. (#72005) · 90dd4c47
  Craig Topper authored Nov 13, 2023
  90dd4c47
- [SelectionDAG] Disable FastISel for swiftasync functions (#70741) · 83729e67
  Felipe de Azevedo Piovezan authored Nov 13, 2023
  83729e67
- [RISCV][CodeGenPrepare] Remove duplicated transform for zext. NFC. (#72053) · d64d5ea1
  Yingwei Zheng authored Nov 13, 2023
  d64d5ea1
- [AArch64] Prevent v1f16 vselect/setcc type expansion. (#72048) · 2238363a
  David Green authored Nov 13, 2023
  2238363a
- [CVP] Infer nneg on existing zext (#72052) · dc6d0773
  Yingwei Zheng authored Nov 13, 2023
  dc6d0773
- [SimplifyCFG] Prevent merging cbranch to cbranch if the branch probability... · f054947c
  Valery Pykhtin authored Nov 13, 2023
  f054947c
- [InstCombine] Require ImmConstant in shift of shift fold · 002da67d
  Nikita Popov authored Nov 13, 2023
  002da67d
- [AMDGPU] Revert "Preliminary patch for divergence driven instruction... · a4196666
  Jay Foad authored Nov 13, 2023
  a4196666
- Recommit changes to global checks (#71171) · e6eda66c
  Henrik G. Olsson authored Nov 13, 2023
  e6eda66c
- [InstCombine] Infer nneg flag from shift users (#71947) · 44cdbef7
  Yingwei Zheng authored Nov 13, 2023
  44cdbef7