Commits · f78687df9b790b4f4177a72cbd25b49d14c437b4 · Roger Ferrer / llvm-epi · GitLab

Aug 26, 2020
- AMDGPU: Don't assert on misaligned DS read2/write2 offsets · f78687df
  Matt Arsenault authored Aug 26, 2020
  f78687df
- AMDGPU/GlobalISel: Tolerate negated control flow intrinsic outputs · 21ccedc2
  Matt Arsenault authored Aug 25, 2020
  21ccedc2
- GlobalISel: Combine G_ADD of G_PTRTOINT to G_PTR_ADD · eb074088
  Matt Arsenault authored Aug 16, 2020
  eb074088
- [AMDGPU][GlobalISel] Eliminate barrier if workgroup size is not greater than wavefront size · 831457c6
  Jay Foad authored Aug 26, 2020
  831457c6
- [Scheduling] Implement a new way to cluster loads/stores · ebf3b188
  QingShan Zhang authored Aug 26, 2020
  ebf3b188
Aug 25, 2020
- AMDGPU/GlobalISel: re-auto-generate some test checks · 8a1926c6
  Jay Foad authored Aug 25, 2020
  
  8a1926c6
- AMDGPU/GlobalISel: Use more accurate legality rules for merge/unmerge · 0d2fe900
  Matt Arsenault authored Aug 22, 2020
  0d2fe900
- AMDGPU/GlobalISel: Fix using unlegalizable values in tests · 984a499f
  Matt Arsenault authored Aug 22, 2020
  984a499f
- AMDGPU/GlobalISel: Apply bitcast load/store hack to pointer vectors · ef8f3b5a
  Matt Arsenault authored Aug 16, 2020
  ef8f3b5a
Aug 24, 2020
- AMDGPU/GlobalISel: Handle AGPRs used for SGPR operands. · 77e5a195
  Matt Arsenault authored Aug 12, 2020
  77e5a195
- AMDGPU: Have a few selection failure tests check both paths · 05a3c884
  Matt Arsenault authored Jul 29, 2020
  05a3c884
- AMDGPU: Add flag to disable promotion of uniform i16 ops · 75e6f0b3
  Matt Arsenault authored Jul 31, 2020
  75e6f0b3
- TableGen/GlobalISel: Allow inst matcher to check multiple opcodes · 116affb1
  Matt Arsenault authored Aug 02, 2020
  116affb1
- [SDAG] Convert FSHL <--> FSHR if the target only supports one of them · a5220676
  Jay Foad authored Aug 24, 2020
  a5220676
- AMDGPU/GlobalISel: Use different technique for sample v3s16 values · bdb25b3c
  Matt Arsenault authored Jul 16, 2020
  bdb25b3c
- AMDGPU/GlobalISel: Add baseline, failing unmerge tests · 9b3222d5
  Matt Arsenault authored Aug 19, 2020
  
  9b3222d5
- AMDGPU/GlobalISel: Start implementing computeKnownBitsForTargetInstr · 70cd9f5b
  Matt Arsenault authored Aug 16, 2020
  70cd9f5b
- GlobalISel: Reduce G_SHL width if source is extension · e1644a37
  Matt Arsenault authored Aug 15, 2020
  e1644a37
- [SelectionDAG] Fix miscompile bug in expandFunnelShift · 7a4e26ad
  Bjorn Pettersson authored Aug 22, 2020
  7a4e26ad
Aug 22, 2020
- GlobalISel: Merge FewerElements for G_BUILD_VECTOR/G_CONCAT_VECTORS · 901e3317
  Matt Arsenault authored Aug 03, 2020
  901e3317
Aug 21, 2020
- [AMDGPU] Avoid sorting stalls in regbank-reassign · 9a9a092e
  Stanislav Mekhanoshin authored Aug 20, 2020
  9a9a092e
- [AMDGPU] Use ds_read/write_b96/b128 when possible for SDag · 0654ff70
  Mirko Brkusanin authored Aug 21, 2020
  0654ff70
- [AMDGPU][GlobalISel] Fix 96 and 128 local loads and stores · d17ea67b
  Mirko Brkusanin authored Aug 21, 2020
  d17ea67b
- [AMDGPU] Reorganize GCN subtarget features for unaligned access · f5cd7ec9
  Mirko Brkusanin authored Aug 21, 2020
  f5cd7ec9
- [AMDGPU] Fix alignment requirements for 96bit and 128bit local loads and stores · 5bd1febe
  Mirko Brkusanin authored Aug 21, 2020
  5bd1febe
- [SelectionDAG] Better legalization for FSHL and FSHR · 0819a641
  Jay Foad authored Mar 31, 2020
  0819a641
- [amdgpu] Add codegen support for HIP dynamic shared memory. · 5257a60e
  Michael Liao authored Jun 24, 2020
  5257a60e
Aug 20, 2020
- CodeGen: Don't drop AA metadata when splitting MachineMemOperands · 79ce9bb3
  Matt Arsenault authored Aug 08, 2020
  79ce9bb3
- AMDGPU/GlobalISel: Legalize odd sized loads with widening · 18b21800
  Matt Arsenault authored Jun 26, 2020
  18b21800
- GlobalISel: Implement fewerElementsVector for G_CONCAT_VECTORS sources · 31adc28d
  Matt Arsenault authored Aug 03, 2020
  31adc28d
Aug 19, 2020
- AMDGPU/GlobalISel: Add some bitcast tests · ff5758fe
  Matt Arsenault authored Aug 19, 2020
  
  ff5758fe
- AMDGPU/GlobalISel: Add selection tests for pointer constants · 386a5ea2
  Matt Arsenault authored Aug 18, 2020
  
  386a5ea2
- Revert "[AMDGPU] Support disassembly for AMDGPU kernel descriptors" · fdf71d48
  Ronak Chauhan authored Aug 19, 2020
  fdf71d48
- [AMDGPU] Support disassembly for AMDGPU kernel descriptors · cacfb02d
  Ronak Chauhan authored Jun 19, 2020
  cacfb02d
- AMDGPU: Implement waterfall loop for MIMG instructions with 256-bit SRsrc · e7081d11
  Changpeng Fang authored Aug 18, 2020
  e7081d11
Aug 18, 2020
- GlobalISel: Implement fewerElementsVector for G_INSERT_VECTOR_ELT · 5a15f662
  Matt Arsenault authored Jul 27, 2020
  5a15f662
- [GlobalISel] Add a combine for ashr(shl x, c), c --> sext_inreg x, c' · 40e269ea
  Amara Emerson authored Aug 14, 2020
  40e269ea
- [GlobalISel][CallLowering] Look through call parameters for flags · 224a8c63
  Jessica Paquette authored Aug 17, 2020
  224a8c63
- AMDGPU/GlobalISel: Select llvm.amdgcn.groupstaticsize · 2f5f5feb
  Matt Arsenault authored Jul 26, 2020
  2f5f5feb
- AMDGPU/GlobalISel: Fix selection of s1/s16 G_[F]CONSTANT · 3ba7777b
  Matt Arsenault authored Jul 25, 2020
  3ba7777b