Commits · f9a8c6a0e50540f68e6740a849a7caf5e4d46ca6 · Roger Ferrer / llvm-epi · GitLab

Apr 10, 2021
- [AMDGPU][CostModel] Refine cost model for control-flow instructions. · 8f4b7e94
  dfukalov authored Feb 16, 2021
  8f4b7e94
Apr 06, 2021
- [KnownBits] Rename KnownBits::computeForMul to KnownBits::mul. NFCI. · ddbb5873
  Simon Pilgrim authored Mar 25, 2021
  ddbb5873
Apr 03, 2021
- [FastISel] Remove kill tracking · 66506582
  Nikita Popov authored Mar 09, 2021
  66506582
Apr 01, 2021
- [ARM] Allow v6m runtime loop unrolling · da98177c
  David Green authored Apr 01, 2021
  da98177c
- [ARM] Remove an unused parameter in ARMWinCOFFObjectWriter. NFC. · 4391d764
  Martin Storsjö authored Mar 30, 2021
  4391d764
- [MC][ARM] add .w suffixes for RSB/RSBS T1 · 52338af5
  Nick Desaulniers authored Apr 01, 2021
  52338af5
- [MC][ARM] add .w suffixes for ORN/ORNS T1 · 1addc231
  Nick Desaulniers authored Apr 01, 2021
  1addc231
Mar 31, 2021
- NFC: Change getIntrinsicInstrCost to return InstructionCost · 2f6f249a
  Sander de Smalen authored Jan 22, 2021
  2f6f249a
- NFC: Change getUserCost to return InstructionCost · 3ccbd4f3
  Sander de Smalen authored Jan 20, 2021
  3ccbd4f3
Mar 30, 2021
- [ARM] Add FeatureHasNoBranchPredictor for Thumb1 cores · 3a6365a4
  David Green authored Mar 30, 2021
  3a6365a4
- [NFC][CodeGen] Tidy up TargetRegisterInfo stack realignment functions · a9968c0a
  Tomas Matheson authored Mar 15, 2021
  a9968c0a
- [ARM] Handle Splats in MVE lane interleaving · d4b3380d
  David Green authored Mar 30, 2021
  d4b3380d
Mar 29, 2021
- [ARM] Extend MVE lane interleaving to handle other non-instruction leaves · 3a68c6d2
  David Green authored Mar 29, 2021
  3a68c6d2
- [ARM] Fix the Changed value in the MVE lane interleaving pass. · 6c88ffed
  David Green authored Mar 28, 2021
  
  6c88ffed
Mar 28, 2021
- [ARM] MVE vector lane interleaving · 7b6f760f
  David Green authored Mar 28, 2021
  7b6f760f
Mar 25, 2021
- [ARM] Revert WhileLoopStartLR to DoLoopStart · d9718960
  David Green authored Mar 25, 2021
  d9718960
Mar 24, 2021
- [ARM] Enable UpperBound unrolling for all loops · 14b2ec93
  David Green authored Mar 24, 2021
  14b2ec93
- [TTI] Return a TypeSize from getRegisterBitWidth. · 55d18b3c
  Sander de Smalen authored Mar 24, 2021
  55d18b3c
Mar 23, 2021
- [ARM] Handle debug instrs in ARM Low Overhead Loop pass · f22b4c71
  Victor Campos authored Mar 19, 2021
  f22b4c71
Mar 21, 2021
- [ARM] VINS f16 pattern · 6d9d2049
  David Green authored Mar 21, 2021
  6d9d2049
Mar 19, 2021
- [ARM] Tone down the MVE scalarization overhead · a2e0312c
  David Green authored Mar 19, 2021
  a2e0312c
Mar 17, 2021
- [ARM] Add VREV MVE shuffle costs · 35e0567d
  David Green authored Mar 17, 2021
  35e0567d
- [TTI] Add a Mask to getShuffleCost · e2935dcf
  David Green authored Mar 17, 2021
  e2935dcf
- [ARM] Use lrdsb for more thumb1 loads. · 402f2cae
  David Green authored Mar 17, 2021
  402f2cae
Mar 15, 2021
- Change void getNoop(MCInst &NopInst) to MCInst getNop() · 5d44c92b
  Fangrui Song authored Mar 15, 2021
  5d44c92b
Mar 12, 2021
- GlobalISel: Fix marking byval arguments as immutable · 6b76d828
  Matt Arsenault authored Mar 06, 2021
  6b76d828
Mar 11, 2021
- [ARM] Move t2DoLoopStart reg alloc hint · bd516d24
  David Green authored Mar 11, 2021
  bd516d24
- [ARM] Improve WLS lowering · fad70c30
  David Green authored Mar 11, 2021
  fad70c30
Mar 09, 2021
- [ARM] Add comment explaining stack frame layout · 8d632ca4
  Oliver Stannard authored Mar 09, 2021
  8d632ca4
Mar 06, 2021
- [MC][ARM] Support .reloc *, BFD_RELOC_{NONE,8,16,32}, * · 59ff9315
  Fangrui Song authored Mar 05, 2021
  59ff9315
Mar 04, 2021
- [objdump][ARM] Use correct offset when printing ARM/Thumb branch targets · aac056c5
  Oliver Stannard authored Mar 02, 2021
  aac056c5
- [ARM] KnownBits for CSINC/CSNEG/CSINV · a968e7b8
  David Green authored Mar 04, 2021
  a968e7b8
Mar 03, 2021
- [ARM] Ensure undef is propagated to CBZ/CBNZ flags · ab280cba
  David Green authored Mar 03, 2021
  ab280cba
Mar 02, 2021
- [AArch64][GlobalISel] Enable use of the optsize predicate in the selector. · 8a316045
  Amara Emerson authored Feb 24, 2021
  8a316045
- [ARM] Use 0, not ZR during ISel for CSINC/INV/NEG · 438c9851
  David Green authored Mar 02, 2021
  438c9851
- [ARM] Add handling of t2LDRSB/t2LDRSH in Constant Island Pass · d6ba8ecb
  David Green authored Mar 02, 2021
  d6ba8ecb
- [ARM] support symbolic expressions as branch target in b.w · c3510505
  Jian Cai authored Mar 01, 2021
  c3510505
Mar 01, 2021
- [ARM] Rename pass to MVETPAndVPTOptimisationsPass · e880f8b8
  David Green authored Mar 01, 2021
  e880f8b8
- GlobalISel: Move splitToValueTypes to generic code · 6c260d3b
  Matt Arsenault authored Feb 28, 2021
  6c260d3b
Feb 28, 2021
- [ARM] VMOVN undef folding · 91ebc4e8
  David Green authored Feb 28, 2021
  91ebc4e8