Commits · 07ed62b7d5514937a50b4af4feaa1969911d142e · Lorenzo Albano / LLVM bpEVL · GitLab

Mar 20, 2021
- [RISCV] Disable (mul (and X, 0xffffffff), (and Y, 0xffffffff)) optimization when Zba is enabled. · 07ed62b7
  Craig Topper authored Mar 20, 2021
  07ed62b7
- [RISCV] Add isel pattern to optimize (mul (and X, 0xffffffff), (and Y, 0xffffffff)) on RV64 · b0d8823a
  Craig Topper authored Mar 20, 2021
  b0d8823a
- [VE] Fix types of multiclass template arguments in TableGen files · 879760c2
  Fangrui Song authored Mar 20, 2021
  879760c2
- [X86] Fix a bug when calculating the ldtilecfg insertion points. · 2327513b
  Wang, Pengfei authored Mar 20, 2021
  2327513b
- [AMDGPU] Add MDT update missing from D98915 · 6c9cac5d
  Carl Ritson authored Mar 20, 2021
  
  6c9cac5d
- [PowerPC][NFC] Do not produce i64 constants in 32-bit mode · ea48bf86
  Nemanja Ivanovic authored Mar 19, 2021
  ea48bf86
- [RISCV] Rename WriteShift/ReadShift scheduler classes to... · d5c1d305
  Craig Topper authored Mar 19, 2021
  d5c1d305
- [AMDGPU] Rename SIInsertSkips Pass · fe5f4c39
  Carl Ritson authored Mar 20, 2021
  fe5f4c39
- [AMDGPU] Merge SIRemoveShortExecBranches into SIPreEmitPeephole · 5df2af8b
  Carl Ritson authored Mar 20, 2021
  5df2af8b
- [AMDGPU] Allow index optimisation in SIPreEmitPeephole for bundles · b76c0902
  Carl Ritson authored Mar 20, 2021
  b76c0902
- [NFC] [PowerPC] Determine Endianness in PPCTargetMachine · 697f90eb
  Anshil Gandhi authored Mar 19, 2021
  697f90eb
Mar 19, 2021
- [AArch64] Fix LowerMGATHER to return the chain result for floating point gathers. · 1066dcb5
  Craig Topper authored Mar 19, 2021
  1066dcb5
- [ARM] Tone down the MVE scalarization overhead · a2e0312c
  David Green authored Mar 19, 2021
  a2e0312c
- [Cost]Canonicalize the cost for logical or/and reductions. · 14ae0cf0
  Alexey Bataev authored Mar 02, 2021
  14ae0cf0
- [RISCV] Add missing bitcasts to the results of lowerINSERT_SUBVECTOR and... · 5d315691
  Craig Topper authored Mar 19, 2021
  5d315691
- [Hexagon] Return an i64 for result 0 from LowerREADCYCLECOUNTER instead of an i32. · 95998b89
  Craig Topper authored Mar 19, 2021
  95998b89
- [RISCV] Lower scalable vector masked loads to intrinsics to match fixed... · 85f3f6b3
  Craig Topper authored Mar 19, 2021
  85f3f6b3
- [RISCV] Maintain fixed-length info when optimizing BUILD_VECTORs · d399b82e
  Fraser Cormack authored Mar 19, 2021
  d399b82e
- [RISCV] Fix missing scalable->fixed-length vector conversion · 550292ec
  Fraser Cormack authored Mar 17, 2021
  550292ec
- [AMDGPU] Remove dead glc1 handing in asm parser. NFC. · 57effe22
  Stanislav Mekhanoshin authored Mar 19, 2021
  
  57effe22
- [M68k] Replace unknown operand with explicit type · 028d6250
  Ricky Taylor authored Mar 17, 2021
  028d6250
- [PowerPC] Fix the check for 16-bit signed field in peephole · a8697c57
  Nemanja Ivanovic authored Mar 19, 2021
  a8697c57
- [M68k] Convert register Aliases to AltNames · cd442157
  Ricky Taylor authored Mar 11, 2021
  cd442157
- [M68k] Introduce DReg bead · 51884c6b
  Ricky Taylor authored Mar 11, 2021
  51884c6b
- [AMDGPU] Remove some redundant code. NFC. · 5a5a5312
  Jay Foad authored Mar 19, 2021
  5a5a5312
- [AMDGPU] Skip building some IR if it won't be used. NFC. · 5dd5ddcb
  Jay Foad authored Mar 18, 2021
  
  5dd5ddcb
- [AMDGPU] Sink Intrinsic::getDeclaration calls to where they are used. NFC. · c96dfe0d
  Jay Foad authored Mar 18, 2021
  
  c96dfe0d
- [NVPTX] Fix warning, remove extra ";" [NFC] · 6d22ba48
  Mikael Holmen authored Mar 19, 2021
  6d22ba48
- [X86] Fix -Wunused-function in -DLLVM_ENABLE_ASSERTIONS=off builds · c241659d
  Fangrui Song authored Mar 18, 2021
  
  c241659d
- [RISCV] Spilling for Zvlsseg registers. · aa8d33a6
  Hsiangkai Wang authored Mar 15, 2021
  aa8d33a6
- [RISCV] Correct the output chain in lowerFixedLengthVectorMaskedLoadToRVV · c9861f72
  Craig Topper authored Mar 18, 2021
  c9861f72
- Recommit "[AArch64][GlobalISel] Fold constants into G_GLOBAL_VALUE" · 0ca83730
  Jessica Paquette authored Mar 18, 2021
  0ca83730
Mar 18, 2021
- [AMDGPU] Remove cpol, tfe, and swz from MUBUF patterns · edd6da10
  Stanislav Mekhanoshin authored Mar 15, 2021
  edd6da10
- [WebAssembly] Finalize SIMD names and opcodes · f5764a86
  Thomas Lively authored Mar 18, 2021
  f5764a86
- [WebAssembly] Remove experimental SIMD instructions · 2f2ae08d
  Thomas Lively authored Mar 18, 2021
  2f2ae08d
- [WebAssembly] Remove unimplemented-simd target feature · 8638c897
  Thomas Lively authored Mar 18, 2021
  8638c897
- [llvm][AArch64][SVE] Lower fixed length vector fabs · 0d6482a7
  Peter Waller authored Mar 11, 2021
  0d6482a7
- [AMDGPU] Support SCC on buffer atomics · 961e4384
  Stanislav Mekhanoshin authored Mar 16, 2021
  961e4384
- [AMDGPU] Remove unused template parameters of MUBUF_Real_AllAddr_vi · 3f37c282
  Stanislav Mekhanoshin authored Mar 17, 2021
  3f37c282
- [amdgpu] Update med3 combine to skip i64 · 253f804d
  Jon Chesterfield authored Mar 18, 2021
  253f804d