The logic here is the same for `add` so reuse the existing helper
`isNonZeroAdd`

Alive2 Link:
    https://alive2.llvm.org/ce/z/mhKvC5

Reviewed By: nikic

Differential Revision: https://reviews.llvm.org/D149414

The logic here is the same for normal `(sub X, Y)`, so just reused
`isNonZeroSub`.

Alive2 Link:
    https://alive2.llvm.org/ce/z/9kSkMv

Reviewed By: nikic

Differential Revision: https://reviews.llvm.org/D149412

`(sshl/ushl X, Y) != 0` -> `X != 0`

Alive2 Links
    https://alive2.llvm.org/ce/z/4WLM2p
    https://alive2.llvm.org/ce/z/BHFng4

Reviewed By: nikic

Differential Revision: https://reviews.llvm.org/D149411

for `cttz` if `X[0]` is non-zero, then the expression is non-zero.
for `ctlz` if `X[SignBit]` is non-zero, then the expression in
non-zero.

Alive2 Links:
    cttz (false): https://alive2.llvm.org/ce/z/ySQzbg
    cttz (true): https://alive2.llvm.org/ce/z/auiTCJ
    ctlz (false): https://alive2.llvm.org/ce/z/yk3sTJ
    ctlz (true): https://alive2.llvm.org/ce/z/-JuDty

Reviewed By: nikic

Differential Revision: https://reviews.llvm.org/D149410

We where missing these cases so something like:
`(bitcast to i32 (or v216 x, <2, 1>))`

would not be found to be non-zero.

Reviewed By: nikic

Differential Revision: https://reviews.llvm.org/D149409

Reviewed By: nikic

Differential Revision: https://reviews.llvm.org/D149408

Reviewed By: nikic

Differential Revision: https://reviews.llvm.org/D149407

Reviewed By: nikic

Differential Revision: https://reviews.llvm.org/D149406

Reviewed By: #libc, Mordante

Differential Revision: https://reviews.llvm.org/D149545

During the review of D140653 it was suggested to use vector in
__retarget_buffer instead of manually managing the memory. Due to the
requirements of the Standard it turns out format needs to include vector
leading to a cycle. Therefore switching back to manual memory
management.

This is a preparation to fix https://llvm.org/PR61314

Reviewed By: #libc, ldionne

Differential Revision: https://reviews.llvm.org/D148826

Move calls of collect* helpers closer to where the cost-model is used.
Should help simplifying D142669 & D142670.

Differential Revision: https://reviews.llvm.org/D142674

This reverts commit d775fc39.

The patch is wrong wrt undef and the author didn't fix it after 2 weeks.

Differential Revision: https://reviews.llvm.org/D149101

[LegalizeVectorOps][RISCV] Support condition code legalization for ISD::STRICT_FSETCC/FSETCCS during LegalizeVectorOps.

Switch RISC-V to legalize during LegalizeVectorOps instead of
LegalizeDAG. LegalizeDAG uses the OpVT for legalize action while
LegalizeVectorOps uses the result VT. We really should fix that.

This AND immediately gets legalized to RISCVISD::VMAND_VL and we don't
yet have DAG combine to optimize that away. So this is a quick fix to
improve generated code.

The old LoopUnswitch pass unswitched selects, but the changes were never
ported to the new SimpleLoopUnswitch.

We unswitch by turning:

```
S = select %cond, %a, %b
```

into:

```
head:
br %cond, label %then, label %tail

then:
br label %tail

tail:
S = phi [ %a, %then ], [ %b, %head ]
```

Unswitch selects are always nontrivial, since the successors do not exit
the loop and the loop body always needs to be cloned.

Differential Revision: https://reviews.llvm.org/D138526



Co-authored-by: Sergey Kachkov <sergey.kachkov@syntacore.com>

Reviewed By: ldionne, #libc

Spies: arichardson, libcxx-commits, miyuki

Differential Revision: https://reviews.llvm.org/D143161

Reviewed By: ldionne, #libc

Spies: libcxx-commits, arichardson

Differential Revision: https://reviews.llvm.org/D141888

This reverts commit 176cc70a.

Build is broken after ee9cbe35.

This reverts commit ee9cbe35.

I've been told this cauess a namespace clash in lld.

Instruction selection was failing when trying to zero extend a value
loaded from a PC-relative address. This adds support for zero extension
using the "program counter indirect with displacement" addressing mode.
It also adds a test with code that was previously failing to compile.

This fixes a compile error in Rust's libcore.

Differential Revision: https://reviews.llvm.org/D149034

Change the example to match how this op is actually printed. Do not use
'smart quotes' in the description.

Reviewed By: jpienaar

Differential Revision: https://reviews.llvm.org/D149535

ISD::CondCode is a separate num space from opcodes. isOperationLegalOrCustom
should take an opcode.

Reviewed By: barannikov88

Differential Revision: https://reviews.llvm.org/D149528

RISCVTargetParser.h has a dependency on a tablegen generated file.

Using RISCVISAInfo.h instead avoids this dependency.

We just need this constant somewhere visible to the frontend and
backend and I'm trying to avoid adding a header just for it.

Need to find a better home for RISCV::RVVBitsPerBlock to remove
this dependency. This just a quick fix to fix the build.

The highest address the object can start is ObjSize bytes before the
end (unsigned max value). If this value is not a multiple of the
alignment, the last possible start value is the next lowest multiple
of the alignment. Note: The computations cannot overflow,
because if they would there's no possible start address for the
object.

At the moment, this is limited to GlobalVariables, because I could not
find a API similar to getObjectSize to also get the alignment of the
object. With such an API, this can be generalized to general addresses.

Reviewed By: nikic

Differential Revision: https://reviews.llvm.org/D149483

This uses the patterns defined in MVE_TwoOpPattern to add predicated patterns
for vshls/u instructions.

Differnetial Revision: https://reviews.llvm.org/D149366