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  1. Nov 16, 2016
  2. Nov 15, 2016
  3. Nov 11, 2016
  4. Nov 10, 2016
    • Rafael Espindola's avatar
      Parse relocations only once. · 9f0c4bb7
      Rafael Espindola authored
      Relocations are the last thing that we wore storing a raw section
      pointer to and parsing on demand.
      
      With this patch we parse it only once and store a pointer to the
      actual data.
      
      The patch also changes where we store it. It is now in
      InputSectionBase. Not all sections have relocations, but most do and
      this simplifies the logic. It also means that we now only support one
      relocation section per section. Given that that constraint is
      maintained even with -r with gold bfd and lld, I think it is OK.
      
      llvm-svn: 286459
      9f0c4bb7
    • Eugene Leviant's avatar
      [ELF] Convert .got.plt section to input section · 41ca327b
      Eugene Leviant authored
      Differential revision: https://reviews.llvm.org/D26349
      
      llvm-svn: 286443
      41ca327b
    • George Rimar's avatar
      [ELF] - Implemented --symbol-ordering-file option. · 1a33c0f2
      George Rimar authored
      Patch allows to pass a symbols file to linker.
      LLD will map symbols to sections and sort sections
      in output according to symbol ordering file.
      
      That can help to reduce the startup time and/or
      amount of pagefaults during startup.
      
      Also, interesting benchmark result was produced by Rafael Espíndola. 
      After applying the symbols file for clang he timed compiling 
      X86MCTargetDesc.ii to an object file.  
      
      The page faults went from just
      56,988 to 56,946 since most faults are not in the binary.
      Running time went from 4.403053515 to 4.178112244. 
      The speedup seems to be because of better cache
      locality.
      
      Differential revision: https://reviews.llvm.org/D26130
      
      llvm-svn: 286440
      1a33c0f2
  5. Nov 09, 2016
    • Simon Atanasyan's avatar
      [ELF][MIPS] Convert .reginfo and .MIPS.options sections to synthetic input sections · ce02cf00
      Simon Atanasyan authored
      Previously, we have both input and output sections for .reginfo and
      .MIPS.options. Now for each such sections we have one synthetic input
      sections: MipsReginfoSection and MipsOptionsSection respectively.
      
      Both sections are handled as regular sections until the control reaches
      Writer. Writer then aggregates all sections whose type is SHT_MIPS_REGINFO
      or SHT_MIPS_OPTIONS to create a single synthesized input section. In that
      moment Writer also save GP0 value to the MipsGp0 field of the corresponding
      ObjectFile. This value required for R_MIPS_GPREL16 and R_MIPS_GPREL32
      relocations calculation.
      
      Differential revision: https://reviews.llvm.org/D26444
      
      llvm-svn: 286397
      ce02cf00
    • Rafael Espindola's avatar
      Split Header into individual fields. · 04a2e348
      Rafael Espindola authored
      This is similar to what was done for InputSection.
      
      With this the various fields are stored in host order and only
      converted to target order when writing.
      
      llvm-svn: 286327
      04a2e348
  6. Nov 08, 2016
  7. Nov 05, 2016
    • Simon Atanasyan's avatar
      [ELF][MIPS] N32 ABI support · 9e0297b8
      Simon Atanasyan authored
      In short the patch introduces support for linking object file conform
      MIPS N32 ABI [1]. This ABI is similar to N64 ABI but uses 32-bit
      pointer size.
      
      The most non-trivial requirement of this ABI is one more relocation
      packing format. N64 ABI puts multiple relocation type into the single
      relocation record. The N32 ABI uses series of successive relocations
      with the same offset for this purpose. In this patch, new function
      `mergeMipsN32RelTypes` handle this case and "convert" N32 relocation to
      the N64 relocation so the rest of the code keep unchanged.
      
      For now, linker does not support series of relocations applied to sections
      without SHF_ALLOC bit. Probably later I will add the support or insert
      some sort of assert into the `relocateNonAlloc` routine to catch this
      case.
      
      [1] ftp://www.linux-mips.org/pub/linux/mips/doc/ABI/MIPS-N32-ABI-Handbook.pdf
      
      Differential revision: https://reviews.llvm.org/D26298
      
      llvm-svn: 286052
      9e0297b8
  8. Nov 03, 2016
  9. Nov 02, 2016
  10. Nov 01, 2016
  11. Oct 27, 2016
  12. Oct 26, 2016
  13. Oct 25, 2016
    • Rafael Espindola's avatar
      Delete getSectionHdr. · 58139d17
      Rafael Espindola authored
      We were fairly inconsistent as to what information should be accessed
      with getSectionHdr and what information (like alignment) was stored
      elsewhere.
      
      Now all section info has a dedicated getter. The code is also a bit
      more compact.
      
      llvm-svn: 285079
      58139d17
  14. Oct 21, 2016
    • Simon Atanasyan's avatar
      [ELF][MIPS] Put local GOT entries accessed via a 16-bit index first · bed04bf1
      Simon Atanasyan authored
      Some MIPS relocations used to access GOT entries are able to manipulate
      16-bit index. The other ones like R_MIPS_CALL_HI16/LO16 can handle
      32-bit indexes. 16-bit relocations are generated by default. The 32-bit
      relocations are generated by -mxgot flag passed to compiler. Usually
      these relocation are not mixed in the same code but files like crt*.o
      contain 16-bit relocations so even if all "user's" code compiled with
      -mxgot flag a few 16-bit relocations might come to the linking phase.
      
      Now LLD does not differentiate local GOT entries accessed via a 16-bit
      and 32-bit indexes. That might lead to relocation's overflow if 16-bit
      entries are allocated to far from the beginning of the GOT.
      
      The patch introduces new "part" of MIPS GOT dedicated to the local GOT
      entries accessed by 32-bit relocations. That allows to put local GOT
      entries accessed via a 16-bit index first and escape relocation's overflow.
      
      Differential revision: https://reviews.llvm.org/D25833
      
      llvm-svn: 284809
      bed04bf1
  15. Oct 20, 2016
  16. Oct 06, 2016
  17. Sep 29, 2016
  18. Sep 23, 2016
    • Peter Smith's avatar
      [ARM] ARM TLS shouldn't use relaxations · fde6213f
      Peter Smith authored
      The ARM TLS relocations are placed on literal data and not the 
      code-sequence, it is therefore not possible to implement the relaxTls* 
      functions. This change updates handleMipsTlsRelocation() to
      handleNoRelaxTlsRelocation() and incorporates ARM as well as Mips.
      
      The ARM support in handleNoRelaxTlsRelocation() currently needs to ouput
      the module index dynamic relocation in all cases as it is relying on the 
      dynamic linker to set the module index in the got.
      
      Should address PR30218
      
      Differential Revision: https://reviews.llvm.org/D24827
      
      llvm-svn: 282250
      fde6213f
  19. Sep 12, 2016
  20. Sep 08, 2016
  21. Sep 07, 2016
  22. Sep 06, 2016
  23. Sep 01, 2016
  24. Aug 22, 2016
  25. Aug 19, 2016
  26. Aug 18, 2016
    • Petr Hosek's avatar
      [ELF] Improve error reporting for relocations · 4071b1ba
      Petr Hosek authored
      We should always include symbol name when reporting relocations
      error to simplify debugging of these issues. Without symbol names
      users have to manually investigate which of the libraries contain
      invalid relocations which can be cumbersome when linking multiple
      libraries.
      
      Differential Revision: https://reviews.llvm.org/D23690
      
      llvm-svn: 279162
      4071b1ba
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