Summary: Quick fix

Reviewers: zturner, uweigand

Subscribers: llvm-commits

Differential Revision: https://reviews.llvm.org/D33014

llvm-svn: 302573

Use variadic templates instead of relying on <cstdarg> + sentinel.

This enforces better type checking and makes code more readable.

Differential revision: https://reviews.llvm.org/D32550

llvm-svn: 302572

Use variadic templates instead of relying on <cstdarg> + sentinel.
This enforces better type checking and makes code more readable.

Differential Revision: https://reviews.llvm.org/D32541

llvm-svn: 302571

Test was already marked as failing for mips64el. Now that it's being
tested on mips64, it has to be XFAILed there as well.

llvm-svn: 302570

This test was broken in r302558.

Differential Revision: https://reviews.llvm.org/D33015

llvm-svn: 302569

Summary: computeKnownBitsForTargetNode was not defined for Lanai which resulted in additional AND's with 0x1 for the output of SETCC instructions.

Reviewers: eliben, majnemer

Reviewed By: majnemer

Subscribers: llvm-commits

Differential Revision: https://reviews.llvm.org/D29605

llvm-svn: 302568

Test is XPASSing, so remove the XFAIL marker.

llvm-svn: 302567

Thanks to Eli for pointing out in a post-commit review comment.

llvm-svn: 302566

Handle some more relocation types in
RuntimeDyldELF::resolveSystemZRelocation

This fixes a number of failing LLDB test cases.

llvm-svn: 302565

Adds support for the ORIGIN and LENGTH linker script built in functions.

  ORIGIN(memory) Return the origin of the memory region
  LENGTH(memory) Return the length of the memory region

Redo of D29775 for refactored linker script parsing.

Patch by Robert Clarke

Differential Revision: https://reviews.llvm.org/D32934

llvm-svn: 302564

This test case works fine on SystemZ as well.

llvm-svn: 302563

This commit made ubsan use the fast unwinder.  On SystemZ this requires
test cases to be compiled with -mbackchain.  That was already done for
asan, but not ubsan.  Add the flag for ubsan as well.

llvm-svn: 302562

GCC 4.9.2 likes the specialize one of the memcpys in msan_interceptors.cc,
leading to test failure.

llvm-svn: 302561

The check for valid start function was inverted.  Added a new
test in test/Object to check this case and fixed the existing
tests in for ObjectYAML.

Differential Revision: https://reviews.llvm.org/D32986

llvm-svn: 302560

Now provided in lwpintrin.h

llvm-svn: 302559

Add the toolchain installation directory to the program
path so that lld can be found.

Change -flavor to wasm.  Although this new flavor hasn't
yet landed in upstream lld yet there are no point in
passing wasm objects the gnu flavor.

Differential Revision: https://reviews.llvm.org/D32976

llvm-svn: 302558

LWP / lwpintrin.h is now supported

llvm-svn: 302557

Green dragon had a green stage2 modules bot for a long time now[1] and
it is time to retire it and make a modules build the default for
Apple-style stage2 builds.

This patch turns on LLVM_ENABLE_MODULES.

[1] http://green.lab.llvm.org/green/job/clang-stage2-cmake-modulesRDA_build/
rdar://problem/28672159

Differential Revision: https://reviews.llvm.org/D32603

llvm-svn: 302556

Reverting
  Modified MipsABIInfo::classifyArgumentType so that it now coerces
  aggregate structures only if the size of said aggregate is less than 16/64
  bytes, depending on the ABI.
as it broke clang-with-lto-ubuntu builder.

llvm-svn: 302555

llvm-svn: 302554

--This line, and those below, will be igored--

A    utils/vscode
A    utils/vscode/README
A    utils/vscode/tablegen
A    utils/vscode/tablegen/.vscode
A    utils/vscode/tablegen/.vscode/launch.json
A    utils/vscode/tablegen/CHANGELOG.md
A    utils/vscode/tablegen/README.md
A    utils/vscode/tablegen/language-configuration.json
A    utils/vscode/tablegen/package.json
A    utils/vscode/tablegen/syntaxes
A    utils/vscode/tablegen/syntaxes/TableGen.tmLanguage
A    utils/vscode/tablegen/vsc-extension-quickstart.md

llvm-svn: 302553

The way we currently define congruency for two PHIExpression(s) is:

1) The operands to the phi functions are congruent
2) The PHIs are defined in the same BasicBlock.

NewGVN works under the assumption that phi operands are in predecessor
order, or at least in some consistent order. OTOH, is valid IR:

patatino:
  %meh = phi i16 [ %0, %winky ], [ %conv1, %tinky ]
  %banana = phi i16 [ %0, %tinky ], [ %conv1, %winky ]
  br label %end

and the in-memory representations of the two SSA registers have an
inconsistent order. This violation of NewGVN assumptions results into
two PHIs found congruent when they're not. While we think it's useful
to have always a consistent order enforced, let's fix this in NewGVN
sorting uses in predecessor order before creating a PHI expression.

Differential Revision:  https://reviews.llvm.org/D32990

llvm-svn: 302552

The description says it returns the number of words needed to represent the results. But the way it was coded it always returns (lhsWords + rhsWords) or (lhsWords + rhsWords - 1). But the result could be even smaller than that and it wouldn't tell you.

No one uses the result today so rather than try to fix it, just remove it.

llvm-svn: 302551

llvm-svn: 302550

This patch adds more patterns that a reasonable person might write that can be compiled to BZHI.

This adds support for

(~0U >> (32 - b)) & a;

and

a << (32 - b) >> (32 - b);

This was inspired by the code in APInt::clearUnusedBits.

This can pass an index of 32 to the bzhi instruction which a quick test of Haswell hardware shows will not mask any bits. Though the description text in the Intel manual says the "index is saturated to OperandSize-1". The pseudocode in the same manual indicates no bits will be zeroed for this case.

I think this is still missing cases where the subtract portion is an 8-bit operation.

Differential Revision: https://reviews.llvm.org/D32616

llvm-svn: 302549

The comment says to avoid the case where zero bits are shifted into the truncated value, 
but the code checks that the shift is smaller than the truncated value instead of the 
number of bits added by the sign extension. Fixing this allows a shift by more than the 
value size to be introduced, which is undefined behavior, so the shift is capped at the 
value size minus one, which has the expected behavior of filling the value with the sign 
bit.

Patch by Jacob Young!

Differential Revision: https://reviews.llvm.org/D32285

llvm-svn: 302548

Modified MipsABIInfo::classifyArgumentType so that it now coerces aggregate
structures only if the size of said aggregate is less than 16/64 bytes,
depending on the ABI.

Patch by Stefan Maksimovic.

Differential Revision: https://reviews.llvm.org/D32900

llvm-svn: 302547

for scalar masked instructions only the lower bit of the mask is relevant. so for constant masks we should either do an unmasked operation or no operation, depending on the value of the lower bit.
This patch handles cases where the lower bit is '1'.

Differential Revision: https://reviews.llvm.org/D32805

llvm-svn: 302546

rdar://32074504

llvm-svn: 302545

This re-lands r302483. It was not the cause of PR32977.

llvm-svn: 302544

This re-lands commit r302461. It was not the cause of PR32977.

llvm-svn: 302543

That test update was for r302469, which was reverted in r302533 due to PR32977.

llvm-svn: 302542

llvm-svn: 302541

`__builtin_available`

This commit allows us to use the macOS/iOS/tvOS/watchOS platform names in
`@available`/`__builtin_available`.

rdar://32067795

Differential Revision: https://reviews.llvm.org/D33000

llvm-svn: 302540

Now both emitLeadingFence and emitTrailingFence take the instruction
itself, instead of taking IsLoad/IsStore pairs.
Instruction::mayReadFromMemory and Instrucion::mayWriteToMemory are used
for determining those two booleans.

The instruction argument is also useful for later D32763, in
emitTrailingFence. For emitLeadingFence, it seems to have cleaner
interface with the proposed change.

Differential Revision: https://reviews.llvm.org/D32762

llvm-svn: 302539

Summary:
This change optimizes several aspects of the checksum used for chunk headers.

First, there is no point in checking the weak symbol `computeHardwareCRC32`
everytime, it will either be there or not when we start, so check it once
during initialization and set the checksum type accordingly.

Then, the loading of `HashAlgorithm` for SSE versions (and ARM equivalent) was
not optimized out, while not necessary. So I reshuffled that part of the code,
which duplicates a tiny bit of code, but ends up in a much cleaner assembly
(and faster as we avoid an extraneous load and some calls).

The following code is the checksum at the end of `scudoMalloc` for x86_64 with
full SSE 4.2, before:
```
mov     rax, 0FFFFFFFFFFFFFFh
shl     r10, 38h
mov     edi, dword ptr cs:_ZN7__scudoL6CookieE ; __scudo::Cookie
and     r14, rax
lea     rsi, [r13-10h]
movzx   eax, cs:_ZN7__scudoL13HashAlgorithmE ; __scudo::HashAlgorithm
or      r14, r10
mov     rbx, r14
xor     bx, bx
call    _ZN7__scudo20computeHardwareCRC32Ejm ; __scudo::computeHardwareCRC32(uint,ulong)
mov     rsi, rbx
mov     edi, eax
call    _ZN7__scudo20computeHardwareCRC32Ejm ; __scudo::computeHardwareCRC32(uint,ulong)
mov     r14w, ax
mov     rax, r13
mov     [r13-10h], r14
```
After:
```
mov     rax, cs:_ZN7__scudoL6CookieE ; __scudo::Cookie
lea     rcx, [rbx-10h]
mov     rdx, 0FFFFFFFFFFFFFFh
and     r14, rdx
shl     r9, 38h
or      r14, r9
crc32   eax, rcx
mov     rdx, r14
xor     dx, dx
mov     eax, eax
crc32   eax, rdx
mov     r14w, ax
mov     rax, rbx
mov     [rbx-10h], r14
```

Reviewers: dvyukov, alekseyshl, kcc

Reviewed By: alekseyshl

Subscribers: aemerson, rengolin, llvm-commits

Differential Revision: https://reviews.llvm.org/D32971

llvm-svn: 302538

llvm-svn: 302537

llvm-svn: 302536

ARMRegisterBankInfo.h requires LLVM_BUILD_GLOBAL_ISEL to be defined. If it is not defined, then ARMGenRegisterBank.inc is not table generated and the inclusion of this header causes the build to fail.

llvm-svn: 302535

llvm-svn: 302534