- May 12, 2021
-
-
Qiu Chaofan authored
This commit brought build break in some f128 related tests. But that's not the root cause. There exists some differences between Clang and GCC's definition for 128-bit float types on PPC, so macros/functions in glibc may not work with clang -mfloat128 well. We need to handle this carefully and reland it.
-
Tomas Matheson authored
Based on the same for AArch64: 4751cadc At -O0, the fast register allocator may insert spills between the ldrex and strex instructions inserted by AtomicExpandPass when expanding atomicrmw instructions in LL/SC loops. To avoid this, expand to cmpxchg loops and therefore expand the cmpxchg pseudos after register allocation. Required a tweak to ARMExpandPseudo::ExpandCMP_SWAP to use the 4-byte encoding of UXT, since the pseudo instruction can be allocated a high register (R8-R15) which the 2-byte encoding doesn't support. However, the 4-byte encodings are not present for ARM v8-M Baseline. To enable this, two new pseudos are added for Thumb which are only valid for v8mbase, tCMP_SWAP_8 and tCMP_SWAP_16. The previously committed attempt in D101164 had to be reverted due to runtime failures in the test suites. Rather than spending time fixing that implementation (adding another implementation of atomic operations and more divergence between backends) I have chosen to follow the approach taken in D101163. Differential Revision: https://reviews.llvm.org/D101898 Depends on D101912
-
Tomas Matheson authored
Differential Revision: https://reviews.llvm.org/D101912
-
Alex Orlov authored
This fixes the following bugs: https://bugs.llvm.org/show_bug.cgi?id=43935 Reviewed By: jhenderson Differential Revision: https://reviews.llvm.org/D102258
-
Djordje Todorovic authored
-
Guillaume Chatelet authored
This is a roll forward of D101895 with two additional fixes: Original Patch description: > This is a follow up on D101524 which: > > - simplifies cpu features detection and usage, > - flattens target dependent optimizations so it's obvious which implementations are generated, > - provides an implementation targeting the host (march/mtune=native) for the mem* functions, > - makes sure all implementations are unittested (provided the host can run them). Additional fixes: - Fix uninitialized ALL_CPU_FEATURES - Use non pseudo microarch as it is only supported from Clang 12 on Differential Revision: https://reviews.llvm.org/D102233
-
Dmitry Vyukov authored
I was running: $ ninja check-sanitizer check-msan check-asan \ check-tsan check-lsan check-ubsan check-cfi \ check-profile check-memprof check-xray check-hwasan but missed check-scudo... Differential Revision: https://reviews.llvm.org/D102314
-
Ulysse Beaugnon authored
DialectAsmParser already allows converting an llvm::SMLoc location to a mlir::Location location. This commit adds the same functionality to OpAsmParser. Implementation is copied from DialectAsmParser. Reviewed By: rriddle Differential Revision: https://reviews.llvm.org/D102165
-
Dumitru Potop authored
First step in adding alignment as an attribute to MLIR global definitions. Alignment can be specified for global objects in LLVM IR. It can also be specified as a named attribute in the LLVMIR dialect of MLIR. However, this attribute has no standing and is discarded during translation from MLIR to LLVM IR. This patch does two things: First, it adds the attribute to the syntax of the llvm.mlir.global operation, and by doing this it also adds accessors and verifications. The syntax is "align=XX" (with XX being an integer), placed right after the value of the operation. Second, it allows transforming this operation to and from LLVM IR. It is checked whether the value is an integer power of 2. Reviewed By: ftynse, mehdi_amini Differential Revision: https://reviews.llvm.org/D101492
-
Dmitry Vyukov authored
Add missing includes and use SYS_pipe2 instead of SYS_pipe as it's not present on some arches. Differential Revision: https://reviews.llvm.org/D102311
-
Martin Storsjö authored
This matches how they are defined on X86. This should fix the relative lookup tables pass for COFF, allowing it to be reenabled. Differential Revision: https://reviews.llvm.org/D102217
-
Dmitry Vyukov authored
We have some significant amount of duplication around CheckFailed functionality. Each sanitizer copy-pasted a chunk of code. Some got random improvements like dealing with recursive failures better. These improvements could benefit all sanitizers, but they don't. Deduplicate CheckFailed logic across sanitizers and let each sanitizer only print the current stack trace. I've tried to dedup stack printing as well, but this got me into cmake hell. So let's keep this part duplicated in each sanitizer for now. Reviewed By: vitalybuka Differential Revision: https://reviews.llvm.org/D102221
-
Qiu Chaofan authored
Reviewed By: nemanjai, steven.zhang Differential Revision: https://reviews.llvm.org/D92815
-
Kristina Bessonova authored
Split a few more debug mode tests missed in D100592. Differential Revision: https://reviews.llvm.org/D102194
-
Dmitry Vyukov authored
setlocale interceptor imitates a write into result, which may be located in .rodata section. This is the only interceptor that tries to do this and I think the intention was to initialize the range for msan. So do that instead. Writing into .rodata shouldn't happen (without crashing later on the actual write) and this traps on my local tsan experiments. Reviewed By: vitalybuka Differential Revision: https://reviews.llvm.org/D102161
-
Vitaly Buka authored
-
Dmitry Vyukov authored
Currently we have: sanitizer_posix_libcdep.cpp:146:27: warning: cast between incompatible function types from ‘__sighandler_t’ {aka ‘void (*)(int)’} to ‘sa_sigaction_t’ 146 | sigact.sa_sigaction = (sa_sigaction_t)SIG_DFL; We don't set SA_SIGINFO, so we need to assign to sa_handler. And SIG_DFL is meant for sa_handler, so this gets rid of both compiler warning, type cast and potential runtime misbehavior. Reviewed By: vitalybuka Differential Revision: https://reviews.llvm.org/D102162
-
Dmitry Vyukov authored
We already declare subset of annotations in test.h. But some are duplicated and declared in tests. Move all annotation declarations to test.h. Reviewed By: vitalybuka Differential Revision: https://reviews.llvm.org/D102152
-
Qiu Chaofan authored
Vector single element update optimization is landed in 2db4979c. But the scope needs restriction. This patch restricts the index to inbounds and vector must be fixed sized. In future, we may use value tracking to relax constant restrictions. Reviewed By: fhahn Differential Revision: https://reviews.llvm.org/D102146
-
Dmitry Vyukov authored
Add a test case reported in: https://github.com/google/sanitizers/issues/1401 and fix it. The code assumes sigwait will process other signals. Reviewed By: vitalybuka Differential Revision: https://reviews.llvm.org/D102057
-
Dmitry Vyukov authored
Add a simple test that uses syscall annotations. Just to ensure at least basic functionality works. Also factor out annotated syscall wrappers into a separate header file as they may be useful for future tests. Reviewed By: vitalybuka Differential Revision: https://reviews.llvm.org/D102223
-
Chia-hung Duan authored
Address the TODO of removing recursion while SSA naming. Reviewed By: mehdi_amini Differential Revision: https://reviews.llvm.org/D102226
-
Vitaly Buka authored
-
Congzhe Cao authored
This is a bugfix in the transformation phase. If the original outer loop header branches to both the inner loop (header) and the outer loop latch, and if there is an lcssa PHI node outside the loop nest, then after interchange the new outer latch will have an lcssa PHI node inserted which has two predecessors, i.e., the original outer header and the original outer latch. Currently the transformation assumes it has only one predecessor (the original outer latch) and crashes, since the inserted lcssa PHI node does not take both predecessors as incoming BBs. Reviewed By: Whitney Differential Revision: https://reviews.llvm.org/D100792
-
Jim Ingham authored
Actually, I don't think this test is going to be stable enough to be worthwhile. Let me see if I can think of a better way to test this.
-
Matt Arsenault authored
This was hardcoding the register class to use for the newly created pointer registers, violating the aligned VGPR requirement.
-
Jim Ingham authored
The gdb-remote tests are a bit artificial, depending on Python threading, and sleeps. So I'm not 100% surprised it doesn't work straight up on another XSsystem.
-
Sam Clegg authored
Don't include the relocation addend when calculating the virtual address of a symbol. Instead just pass the symbol's offset and add the addend afterwards. Without this fix we hit the `offset is outside the section` error in MergeInputSegment::getSegmentPiece. This fixes a real world error we were are seeing in emscripten. Differential Revision: https://reviews.llvm.org/D102271
-
Richard Smith authored
Revert "Fix bad mangling of <data-member-prefix> for a closure in the initializer of a variable at global namespace scope." This reverts commit 697ac15a, for which review was not complete. That change was accidentally pushed when an unrelated change was pushed.
-
Richard Smith authored
I believe Clang's behavior is correct according to the standard here, but this is an unusual situation for which we had no test coverage, so I'm adding some.
-
Richard Smith authored
Fix bad mangling of <data-member-prefix> for a closure in the initializer of a variable at global namespace scope. This implements the direction proposed in https://github.com/itanium-cxx-abi/cxx-abi/pull/126. Differential Revision: https://reviews.llvm.org/D101968
-
Matt Arsenault authored
-
Matt Arsenault authored
This was trying to create a bitcast between different address spaces.
-
Matt Arsenault authored
-
Matt Arsenault authored
Currently the ValueHandler handles both selecting the type and location for arguments, as well as inserting instructions needed to handle them. Split this so that the determination of the argument handling is independent of the function state. Currently the checks for tail call compatibility do not follow the full assignment logic, so it misses cases where arguments require nontrivial legalization. This should help avoid targets ending up in a buggy state where the argument evaluation may change in different contexts.
-
Matt Arsenault authored
We can handle the distinction easily enough in the generic code, and this makes it easier to abstract the selection of type/location from the code to insert code.
-
Jordan Rupprecht authored
This reverts commit 6c570442. It causes assertion errors due to widening atomic loads, and potentially causes miscompile elsewhere too. Repro, also posted to D95543: ``` $ cat repro.ll ; ModuleID = 'repro.ll' source_filename = "repro.ll" target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128" target triple = "x86_64-unknown-linux-gnu" %struct.widget = type { i32 } %struct.baz = type { i32, %struct.snork } %struct.snork = type { %struct.spam } %struct.spam = type { i32, i32 } @global = external local_unnamed_addr global %struct.widget, align 4 @global.1 = external local_unnamed_addr global i8, align 1 @global.2 = external local_unnamed_addr global i32, align 4 define void @zot(%struct.baz* %arg) local_unnamed_addr align 2 { bb: %tmp = getelementptr inbounds %struct.baz, %struct.baz* %arg, i64 0, i32 1 %tmp1 = bitcast %struct.snork* %tmp to i64* %tmp2 = load i64, i64* %tmp1, align 4 %tmp3 = getelementptr inbounds %struct.baz, %struct.baz* %arg, i64 0, i32 1, i32 0, i32 1 %tmp4 = icmp ugt i64 %tmp2, 4294967295 br label %bb5 bb5: ; preds = %bb14, %bb %tmp6 = load i32, i32* %tmp3, align 4 %tmp7 = icmp ne i32 %tmp6, 0 %tmp8 = select i1 %tmp7, i1 %tmp4, i1 false %tmp9 = zext i1 %tmp8 to i8 store i8 %tmp9, i8* @global.1, align 1 %tmp10 = load i32, i32* @global.2, align 4 switch i32 %tmp10, label %bb11 [ i32 1, label %bb12 i32 2, label %bb12 ] bb11: ; preds = %bb5 br label %bb14 bb12: ; preds = %bb5, %bb5 %tmp13 = load atomic i32, i32* getelementptr inbounds (%struct.widget, %struct.widget* @global, i64 0, i32 0) acquire, align 4 br label %bb14 bb14: ; preds = %bb12, %bb11 br label %bb5 } $ opt -O2 repro.ll -disable-output opt: /home/rupprecht/src/llvm-project/llvm/lib/Transforms/Utils/VNCoercion.cpp:496: llvm::Value *llvm::VNCoercion::getLoadValueForLoad(llvm::LoadInst *, unsigned int, llvm::Type *, llvm::Instruction *, const llvm::DataLayout &): Assertion `SrcVal->isSimple() && "Cannot widen volatile/atomic load!"' failed. PLEASE submit a bug report to https://bugs.llvm.org/ and include the crash backtrace. Stack dump: 0. Program arguments: /home/rupprecht/dev/opt -O2 repro.ll -disable-output ... ```
-
Lang Hames authored
-
Leonard Chan authored
These are GCC-compatible multilibs that use the generic Itanium C++ ABI instead of the Fuchsia C++ ABI. Differential Revision: https://reviews.llvm.org/D102030
-
Congzhe Cao authored
This is a bug fix in legality check. When we encounter triangular loops such as the following form: for (int i = 0; i < m; i++) for (int j = 0; j < i; j++), or for (int i = 0; i < m; i++) for (int j = 0; j*i < n; j++), we should not perform interchange since the number of executions of the loop body will be different before and after interchange, resulting in incorrect results. Reviewed By: bmahjour Differential Revision: https://reviews.llvm.org/D101305
-