going to be re-spilled again.

This also helps performance.  Pre-alloc-splitting now seems to be an overall win on SPEC.

llvm-svn: 62834

llvm-svn: 62832

llvm-svn: 62828

llvm-svn: 62827

when there are multiple iterations of the loop.  This fixes PR3375.

llvm-svn: 62822

llvm-svn: 62821

compatibility with VC++.  Patch by Max Burke!

llvm-svn: 62813

to "C ^ 1" is only valid when C is known to be either 0 or 1.  Most of the
similar foldings in this function only handle "i1" types, but this one appears
intentionally written to handle larger integer types.  If C has an integer
type larger than "i1", this needs to check if the high bits of a boolean
are known to be zero.  I also changed the comment to describe this folding as
"C ^ 1" instead of "~C", since that is what the code does and since the latter
would only be valid for "i1" types.  The good news is that most LLVM targets
use TargetLowering::ZeroOrOneBooleanContent so this change will not disable
the optimization; the bad news is that I've been unable to come up with a
testcase to demonstrate the problem.

I have also removed a "FIXME" comment for folding "select C, X, 0" to "C & X",
since the code looks correct to me.  It could be made more aggressive by not
limiting the type to "i1", but that would then require checking for
TargetLowering::ZeroOrNegativeOneBooleanContent.  Similar changes could be
done for the other SELECT foldings, but it was decided to be not worth the
trouble and complexity (see e.g., r44663).

llvm-svn: 62790

Simplify x+0 to x in unsafe-fp-math mode. This avoids a bunch of
redundant work in many cases, because in unsafe-fp-math mode,
ISD::FADD with a constant is considered free to negate, so the
DAGCombiner often negates x+0 to -0-x thinking it's free, when
in reality the end result is -x, which is more expensive than x.

Also, combine x*0 to 0.

This fixes PR3374.

llvm-svn: 62789

llvm-svn: 62788

llvm-svn: 62777

llvm-svn: 62776

corresponding to the "not" and "vnot" PatFrags.  Use the new method
in some places where it seems appropriate.

llvm-svn: 62768

llvm-svn: 62763

Eliminate a couple of fields from TargetRegisterClass: SubRegClasses and SuperRegClasses. These are not necessary. Also eliminate getSubRegisterRegClass and getSuperRegisterRegClass. These are slow and their results can change if register file names change. Just use TargetLowering::getRegClassFor() to get the right TargetRegisterClass instead.

llvm-svn: 62762

llvm-svn: 62761

llvm-svn: 62760

analyses could be run without the caches properly sorted.  This
can fix all sorts of weirdness.  Many thanks to Bill for coming
up with the 'issorted' verification idea.

llvm-svn: 62757

to be supported in the JIT.

llvm-svn: 62730

ASCII IR; loading and storing these can change the
bits of NaNs on some hosts.  Remove or add warnings
at a few other places using host floating point;
this is a bad thing to do in general.

llvm-svn: 62712

llvm-svn: 62710

llvm-svn: 62699

PR3364

llvm-svn: 62697

compatibility with cygwin.  Patch by Jay Foad!

llvm-svn: 62695

special cases after producing the new reduced-width load, because the
new load already has the needed adjustments built into it. This fixes
several bugs due to the special cases, including PR3317.

llvm-svn: 62692

we want to clear %ah to zero before a division, just use a
zero-extending mov to %al. This fixes PR3366.

llvm-svn: 62691

llvm-svn: 62688

llvm-svn: 62681

prototypes, in operand type legalization.  No
functionality change.

llvm-svn: 62680

I accidentally removed this check in an earlier commit, which cause breakage in the pre alloc splitter.

llvm-svn: 62678

Also a few signed comparison fixes.

llvm-svn: 62665

- Ensure that (operation) legalization emits proper FDIV libcall when needed.
- Fix various bugs encountered during llvm-spu-gcc build, along with various
  cleanups.
- Start supporting double precision comparisons for remaining libgcc2 build.
  Discovered interesting DAGCombiner feature, which is currently solved via
  custom lowering (64-bit constants are not legal on CellSPU, but DAGCombiner
  insists on inserting one anyway.)
- Update README.

llvm-svn: 62664

Allow targets to legalize operations (with illegal operands) that produces multiple values. For example, a load with an illegal operand (a load produces two values, a value and chain).

llvm-svn: 62663

unsigned test(unsigned a) {
  return ~a;
}
llvm used to generate:
movl    $4294967295, %eax
xorl    4(%esp), %eax

Now it generates:
movl      4(%esp), %eax
notl      %eax

It's 3 bytes shorter.

llvm-svn: 62661

Besides APFloat, this involved removing code
from two places that thought they knew the
result of frem(0., x) but were wrong.

llvm-svn: 62645

llvm-svn: 62639

llvm-svn: 62638

llvm-svn: 62625

Fix PR3243: a LiveVariables bug. When HandlePhysRegKill is checking whether the last reference is also the last def (i.e. dead def), it should also check if last reference is the current machine instruction being processed. This can happen when it is processing a physical register use and setting the current machine instruction as sub-register's last ref.

llvm-svn: 62617

llvm-svn: 62616