Many targets always use the same bitwise encoding value for physical
registers in all (or most) instructions. Add this mapping to the
.td files and TableGen'erate the information and expose an accessor
in MCRegisterInfo.

patch by Tom Stellard.

llvm-svn: 156829

Besides the weight, we also want to store up to two root registers per
unit. Most units will have a single root, the leaf register they
represent. Units created for ad hoc aliasing get two roots: The two
aliasing registers.

The root registers can be used to compute the set of overlapping
registers.

llvm-svn: 156792

Register units can be used to compute if two registers overlap:

  A overlaps B iff units(A) intersects units(B).

With this change, the above holds true even on targets that use ad hoc
aliasing (currently only ARM). This means that register units can be
used to implement regsOverlap() more efficiently, and the register
allocator can use the concept to model interference.

When there is no ad hoc aliasing, the register units correspond to the
maximal cliques in the register overlap graph. This is optimal, no other
register unit assignment can have fewer units.

With ad hoc aliasing, weird things are possible, and we don't try too
hard to compute the maximal cliques. The current approach is always
correct, and it works very well (probably optimally) as long as the ad
hoc aliasing doesn't have cliques larger than pairs. It seems unlikely
that any target would need more.

llvm-svn: 156763

The ad hoc aliasing specified in the 'Aliases' list in .td files is
currently only used by computeOverlaps(). It will soon be needed to
build accurate register units as well, so build the undirected graph in
CodeGenRegister::buildObjectGraph() instead.

Aliasing is a symmetric relationship with only one direction specified
in the .td files. Make sure both directions are represented in
getExplicitAliases().

llvm-svn: 156762

TableGen creates new register classes and sub-register indices based on
the sub-register structure present in the register bank. So far, it has
been doing that on a per-register basis, but that is not very efficient.

This patch teaches TableGen to compute topological signatures for
registers, and use that to reduce the amount of redundant computation.
Registers get the same TopoSig if they have identical sub-register
structure.

TopoSigs are not currently exposed outside TableGen.

llvm-svn: 156761

TableGen doesn't need to search through the SubRegs map to find an
inverse entry.

llvm-svn: 156690

llvm-svn: 156649

Don't compute the SuperRegs list until the sub-register graph is
completely finished. This guarantees that the list of super-registers is
properly topologically ordered, and has no duplicates.

llvm-svn: 156629

The sub-registers explicitly listed in SubRegs in the .td files form a
tree. In a complicated register bank, it is possible to have
sub-register relationships across sub-trees. For example, the ARM NEON
double vector Q0_Q1 is a tree:

  Q0_Q1 = [Q0, Q1],  Q0 = [D0, D1], Q1 = [D2, D3]

But we also define the DPair register D1_D2 = [D1, D2] which is fully
contained in Q0_Q1.

This patch teaches TableGen to find such sub-register relationships, and
assign sub-register indices to them. In the example, TableGen will
create a dsub_1_dsub_2 sub-register index, and add D1_D2 as a
sub-register of Q0_Q1.

This will eventually enable the coalescer to handle copies of skewed
sub-registers.

llvm-svn: 156587

The .td files specify a tree of sub-registers. Store that tree as
ExplicitSubRegs lists in CodeGenRegister instead of extracting it from
the Record when needed.

llvm-svn: 156555

I initially assumed that the subreg graph was a tree. That may not be true.

llvm-svn: 156524

llvm-svn: 156521

This mapping is for internal use by TableGen. It will not be exposed in
the generated files.

Unfortunately, the mapping is not completely well-defined. The X86 xmm
registers appear with multiple sub-register indices in the ymm
registers. This is because of the odd idempotent sub_sd and sub_ss
sub-register indices. I hope to be able to eliminate them entirely, so
we can require the sub-registers to form a tree.

For now, just place the canonical sub_xmm index in the mapping, and
ignore the idempotents.

llvm-svn: 156519

That's what it does.

llvm-svn: 156518

r145222 "lit/TestRunner.py: [Win32] Introduce WinWaitReleased(f), to wait for file handles to be released by children."
r145223 "lit/TestRunner.py: Use RemoveForce()."
r145381 "lit/TestRunner.py: Try to catch ERROR_FILE_NOT_FOUND, too."
r152916 "lit/TestRunner.py: [Win32] Check all opened_files[] released, rather than (obsoleted) written_files[]."
r153172 "lit/TestRunner.py: [Win32] Rework WinWaitReleased() again! "win32file" from Python Win32 Extensions."

llvm-svn: 156381

optional library support to the llvm-build tool:
 - Add new command line parameter to llvm-build: “--enable-optional-libraries”
 - Add handing of new llvm-build library type “OptionalLibrary”
 - Update Cmake and automake build systems to pass correct flags to llvm-build
   based on configuration

Patch by Dan Malea!

llvm-svn: 156319

Previously, if an instruction definition was missing the mnemonic,
the next line would just assert(). Issue a real diagnostic instead.

llvm-svn: 156263

This is still a topological ordering such that every register class gets
a smaller enum value than its sub-classes.

Placing the smaller spill sizes first makes a difference for the
super-register class bit masks. When looking for a super-register class,
we usually want the smallest possible kind of super-register. That is
now available as the first bit set in the bit mask.

llvm-svn: 156222

This manually enumerated list of super-register classes has been
superceeded by the automatically computed super-register class masks
available through SuperRegClassIterator.

llvm-svn: 156151

TargetRegisterClass now gives access to the necessary tables.

llvm-svn: 156122

This is a pointer into one of the tables used by
getMatchingSuperRegClass(). It makes it possible to use a shared
implementation of that function.

llvm-svn: 156121

The RC->getSubClassMask() pointer now points to a sequence of register
class bit masks. The first bit mask is the normal sub-class mask. The
following masks are super-reg class masks used by
getMatchingSuperRegClass().

llvm-svn: 156120

Many register classes only have a few super-registers, so it is not
necessary to keep individual bit masks for all possible sub-register
indices.

llvm-svn: 156083

llvm-svn: 156080

Some targets have no sub-registers at all. Use the TargetRegisterInfo
versions of composeSubRegIndices(), getSubClassWithSubReg(), and
getMatchingSuperRegClass() for those targets.

llvm-svn: 156075

be used by clang-tblgen.

llvm-svn: 156000

Add ifdef around getSubtargetFeatureName in tablegen output file so that only targets that want the function get it. This prevents other targets from getting an unused function warning.

llvm-svn: 155538

When an instruction match is found, but the subtarget features it
requires are not available (missing floating point unit, or thumb vs arm
mode, for example), issue a diagnostic that identifies what the feature
mismatch is.

rdar://11257547

llvm-svn: 155499

llvm-svn: 155270

llvm-svn: 155234

llvm-svn: 155230

Assembly matchers for instructions with a two-operand form. ARM is full
of these, for example:
  add {Rd}, Rn, Rm  // Rd is optional and is the same as Rn if omitted.

The property TwoOperandAliasConstraint on the instruction definition controls
when, and if, an alias will be formed. No explicit InstAlias definitions
are required.

rdar://11255754

llvm-svn: 155172

llvm-ld is no longer useful and causes confusion and so it is being removed.

* Does not work very well on Windows because it must call a gcc like driver to
  assemble and link.
* Has lots of hard coded paths which are wrong on many systems.
* Does not understand most of ld's options.
* Can be partially replaced by llvm-link | opt | {llc | as, llc -filetype=obj} |
  ld, or fully replaced by Clang.

I know of no production use of llvm-ld, and hacking use should be
replaced by Clang's driver.

llvm-svn: 155147

There's almost always a small number of instruction operands, so
use a SmallVector and save on heap allocations.

llvm-svn: 155143

llvm-svn: 155142

the user has another lit somewhere.

llvm-svn: 155131

Make fast isel use &XXXRegClass instead of XXXRegisterClass. Not a functional change since XXXRegisterClass is just a constant alias of &XXXRegClass, but should probably go away.

llvm-svn: 155104

llvm-svn: 155075

llvm-svn: 155049

StringMap iterators are not deterministic, and that's more important
here than speed or memory.

llvm-svn: 155039