llvm-svn: 108277

This may not be right in all cases, but it's better
than asserting which it was doing before.  PR 7528.

llvm-svn: 108268

LiveInterval::overlapsFrom dereferences end() if it is called on an empty
interval.

It would be reasonable to just return false - an empty interval doesn't overlap
anything, but I want to know who is doing it first.

llvm-svn: 108264

Also, one binary search is enough.

llvm-svn: 108261

they already have one.

This fixes the himenobmtxpa miscompilation on ARM.

The PostRA scheduler got confused by the double memoperand and hoisted a stack
slot load above a store to the same slot.

llvm-svn: 108219

llvm-svn: 108164

llvm-svn: 108130

AggressiveAntiDepBreaker should not be using getPhysicalRegisterRegClass. An
instruction might be using a register that can only be replaced with one from
a subclass of getPhysicalRegisterRegClass.

With this patch we use getMinimalPhysRegClass. This is correct, but
conservative. We should check the uses of the register and select the
largest register class that can be used in all of them.

llvm-svn: 108122

physical register can be allocated in the class of the virtual are sufficient.

I think that the test for virtual registers is more strict than it needs to be,
it should be possible to coalesce two virtual registers the class of one
is a subclass of the other.

llvm-svn: 108118

getMinimalPhysRegClass. It was used to produce spills, and it is better to
use the most specific class if possible.

Update getLoadStoreRegOpcode to handle GR32_AD.

llvm-svn: 108115

intended functionality change.

The avoidance of hoistiing implicitdef seems wrong though.

llvm-svn: 108109

Targets must now implement TargetInstrInfo::copyPhysReg instead. There is no
longer a default implementation forwarding to copyRegToReg.

llvm-svn: 108095

The first one was used just to call isSafeToMoveRegClassDefs. In
general, using a more specific reg class is better, in practice only
x86 implements that method and the results are always the same.

The second one is in FindFreeRegister and is used to check if a register
is in a register class, a much more direct call to contains is better as
it should cover more cases and is faster.

llvm-svn: 108093

assert()s, switching to void-casts. Removed an unneeded Compiler.h include as
a result. There are two other uses in LLVM, but they're not due to assert()s,
so I've left them alone.

llvm-svn: 108088

This doesn't change the behavior of SelectBitcast for X86.

llvm-svn: 108073

correct alignment information, which simplifies ExpandRes_VAARG a bit.

The patch introduces a new alignment information to TargetLoweringInfo. This is
needed since the two natural candidates cannot be used:

* The 's' in target data: If this is set to the minimal alignment of any
  argument, getCallFrameTypeAlignment would return 4 for doubles on ARM for
  example.
* The getTransientStackAlignment method. It is possible for an architecture to
  have argument less aligned than what we maintain the stack pointer.

llvm-svn: 108072

This assumes that the registers can be copied which is probably a safe
assumption.

llvm-svn: 108070

The remaining copyRegToReg calls actually check the return value (shock!), so we
cannot trivially replace them with COPY instructions.

llvm-svn: 108069

llvm-svn: 108062

This also avoids fatal copies from physregs.

llvm-svn: 108061

if a block is split (by a custom inserter), the insert point may be in a
different block than it was originally. This fixes 32-bit llvm-gcc
bootstrap builds, and I haven't been able to reproduce it otherwise.

llvm-svn: 108060

ScheduleDAGEmit, TwoAddressLowering, and PHIElimination.

This switches the bulk of register copies to using COPY, but many less used
copyRegToReg calls remain.

llvm-svn: 108050

at the end of the block.

llvm-svn: 108045

 - Check getBytesToPopOnReturn().
 - Eschew ST0 and ST1 for return values.
 - Fix the PIC base register initialization so that it doesn't ever
   fail to end up the top of the entry block.

llvm-svn: 108039

llvm-svn: 108023

llvm-svn: 108013

llvm-svn: 108012

llvm-svn: 108010

llvm-svn: 108005

llvm-svn: 108001

inserted in a MBB, and return an already inserted MI.

This target API change is necessary to allow foldMemoryOperand to call
storeToStackSlot and loadFromStackSlot when folding a COPY to a stack slot
reference in a target independent way.

The foldMemoryOperandImpl hook is going to change in the same way, but I'll wait
until COPY folding is actually implemented. Most targets only fold copies and
won't need to specialize this hook at all.

llvm-svn: 107991

U    utils/TableGen/FastISelEmitter.cpp
--- Reverse-merging r107943 into '.':
U    test/CodeGen/X86/fast-isel.ll
U    test/CodeGen/X86/fast-isel-loads.ll
U    include/llvm/Target/TargetLowering.h
U    include/llvm/Support/PassNameParser.h
U    include/llvm/CodeGen/FunctionLoweringInfo.h
U    include/llvm/CodeGen/CallingConvLower.h
U    include/llvm/CodeGen/FastISel.h
U    include/llvm/CodeGen/SelectionDAGISel.h
U    lib/CodeGen/LLVMTargetMachine.cpp
U    lib/CodeGen/CallingConvLower.cpp
U    lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
U    lib/CodeGen/SelectionDAG/FunctionLoweringInfo.cpp
U    lib/CodeGen/SelectionDAG/FastISel.cpp
U    lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
U    lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp
U    lib/CodeGen/SelectionDAG/InstrEmitter.cpp
U    lib/CodeGen/SelectionDAG/TargetLowering.cpp
U    lib/Target/XCore/XCoreISelLowering.cpp
U    lib/Target/XCore/XCoreISelLowering.h
U    lib/Target/X86/X86ISelLowering.cpp
U    lib/Target/X86/X86FastISel.cpp
U    lib/Target/X86/X86ISelLowering.h

llvm-svn: 107987

llvm-svn: 107980

This fixes PR7602.

llvm-svn: 107957

This fixes PR7601.

llvm-svn: 107955

llvm-svn: 107950

llvm-svn: 107949

a DBG_VALUE after a terminator, or emitting any instructions before an EH_LABEL.

llvm-svn: 107943

disabled and then never turned back on again.  Adjust some tests, one because
this change avoids an unnecessary instruction, and the other to make it
continue testing what it was intended to test.

llvm-svn: 107941

llvm-svn: 107930