This is possible if there is an undef use when
splitting the vreg during spilling.

Fixes bug 33620.

llvm-svn: 308808

Bitrig code has been merged back to OpenBSD, thus the OS has been abandoned.

Differential Revision: https://reviews.llvm.org/D35707

llvm-svn: 308799

llvm-svn: 308781

For example
  asm ("memw(%0++%1) = %2" : : "r"(addr),"a"(mod),"r"(val) : "memory")

llvm-svn: 308761

-membedded-data changes the location of constant data from the .sdata to
the .rodata section. Previously it was (incorrectly) always located in the
.rodata section.

Reviewers: atanasyan

Differential Revision: https://reviews.llvm.org/D35686

llvm-svn: 308758

test/CodeGen/SystemZ/loop-01.ll was incorrectly updated by r308729.

llvm-svn: 308736

This patch makes LSR generate better code for SystemZ in the cases of memory
intrinsics, Load->Store pairs or comparison of immediate with memory.

In order to achieve this, the following common code changes were made:

 * New TTI hook: LSRWithInstrQueries(), which defaults to false. Controls if
 LSR should do instruction-based addressing evaluations by calling
 isLegalAddressingMode() with the Instruction pointers.
 * In LoopStrengthReduce: handle address operands of memset, memmove and memcpy
 as address uses, and call isFoldableMemAccessOffset() for any LSRUse::Address,
 not just loads or stores.

SystemZ changes:

 * isLSRCostLess() implemented with Insns first, and without ImmCost.
 * New function supportedAddressingMode() that is a helper for TTI methods
 looking at Instructions passed via pointers.

Review: Ulrich Weigand, Quentin Colombet
https://reviews.llvm.org/D35262
https://reviews.llvm.org/D35049

llvm-svn: 308729

We should be able to handle the case where some c1+c2 elements exceed max shift and some don't by performing a clamp after the sum

llvm-svn: 308724

Currently we only support (i32 bitcast(v32i1)) using the AVX2 VPMOVMSKB ymm instruction.

This patch adds support for splitting pre-AVX2 targets into 2 x (V)PMOVMSKB xmm instructions and merging the integer results.

In future we could probably generalize this to handle more cases.

Differential Revision: https://reviews.llvm.org/D35303

llvm-svn: 308723

The bitconverts here had an input type of 128-bits and an output type of 256 bits. The input type should also have been 256 bits.

llvm-svn: 308702

It revealed a bug in the Localizer pass which has now been fixed.

This includes the fix for SUBREG_TO_REG committed separately last time.

llvm-svn: 308688

If the localizer pass puts one of its constants before the label that tells the
unwinder "jump here to handle your exception" then control-flow will skip it,
leaving uninitialized registers at runtime. That's bad.

llvm-svn: 308687

The patch adds support of i128 params lowering. The changes are quite trivial to
support i128 as a "special case" of integer type. With this patch, we lower i128
params the same way as aggregates of size 16 bytes: .param .b8 _ [16].

Currently, NVPTX can't deal with the 128 bit integers:
* in some cases because of failed assertions like
  ValVTs.size() == OutVals.size() && "Bad return value decomposition"
* in other cases emitting PTX with .i128 or .u128 types (which are not valid [1])
  [1] http://docs.nvidia.com/cuda/parallel-thread-execution/index.html#fundamental-types

Differential Revision: https://reviews.llvm.org/D34555
Patch by: Denys Zariaiev (denys.zariaiev@gmail.com)

llvm-svn: 308675

On AMDGPU SGPR spills are really spilled to another register.
The spiller creates the spills to new frame index objects,
which is used as a placeholder.

This will eventually be replaced with a reference to a position
in a VGPR to write to and the frame index deleted. It is
most likely not a real stack location that can be shared
with another stack object.

This is a problem when StackSlotColoring decides it should
combine a frame index used for a normal VGPR spill with
a real stack location and a frame index used for an SGPR.

Add an ID field so that StackSlotColoring has a way
of knowing the different frame index types are
incompatible.

llvm-svn: 308673

llvm-svn: 308672

Summary:
Also enable no-fsmuld for sparcv7 (which doesn't have the
instruction).

The previous code which used a post-processing pass to do this was
unnecessary; disabling the instruction is entirely sufficient.

Reviewers: jacob_hansen, ekedaigle

Subscribers: llvm-commits

Differential Revision: https://reviews.llvm.org/D35576

llvm-svn: 308661

[X86] Allow masks with more than 6 bits set on the x << (y & mask) optimization for the 64-bit memory shifts.

llvm-svn: 308657

[X86] Add test case to demonstrate that we don't allow masks wider than 6 bits in the (shift x, (and y, mask)) patterns for the 64-bit memory form.

We allow wider than 5 bits in the 16 and 32 bit store forms. And we allow wider than 6 bits on the 64-bit regsiter form.:w

I'm assuming this was a mistake made back in r148024.

llvm-svn: 308656

Summary:
When pushing an extension of a constant bitwise operator on a load
into the load, change other uses of the load value if they exist to
prevent the old load from persisting.

Reviewers: spatel, RKSimon, efriedma

Subscribers: llvm-commits

Differential Revision: https://reviews.llvm.org/D35030

llvm-svn: 308618

Summary:
Add missing vector write of vector read reduction, i.e.:

(insert_vector_elt x (extract_vector_elt x idx) idx) to x

Reviewers: spatel, RKSimon, efriedma

Reviewed By: RKSimon

Subscribers: llvm-commits

Differential Revision: https://reviews.llvm.org/D35563

llvm-svn: 308617

Builder clang-x86_64-linux-abi-test apparently failed due
to a spurious error unrelated to the changes r308585
introduced.

llvm-svn: 308612

Test constant folding both on node creation (which already works) and once the input nodes have been folded themselves (not working yet).

llvm-svn: 308611

This patch adds handling of the `long_call`, `far`, and `near`
attributes passed by front-end. The patch depends on D35479.

Differential revision: https://reviews.llvm.org/D35480.

llvm-svn: 308606

This reverts commit 36c6a2ea9669bc3bb695928529a85d12d1d3e3f9 because it
broke the test-suite on the GlobalISel bot.

llvm-svn: 308603

Use predicate matchers introduced in D35492 to match more ISD::SRL constant folds

llvm-svn: 308602

Use predicate matchers introduced in D35492 to match more ISD::SRA constant folds

llvm-svn: 308600

Most combines currently recognise scalar and splat-vector constants, but not non-uniform vector constants.

This patch introduces a matching mechanism that uses predicates to check against BUILD_VECTOR of ConstantSDNode, as well as scalar ConstantSDNode cases.

I've changed a couple of predicates to demonstrate - the combine-shl changes add currently unsupported cases, while the MatchRotate replaces an existing mechanism.

Differential Revision: https://reviews.llvm.org/D35492

llvm-svn: 308598

Builder clang-x86_64-linux-abi-test seems to fail after this change

llvm-svn: 308597

Introduced FSELECT node necesary when lowering ISD::SELECT
which has i32, f64, f64 as its operands.
SEL_D instruction required that its output and first operand
of a SELECT node, which it used, have matching types.
MTC1_D64 node introduced to aid FSELECT lowering.

This fixes machine verifier errors on following tests:
CodeGen/Mips/llvm-ir/select-dbl.ll
CodeGen/Mips/llvm-ir/select-flt.ll
CodeGen/Mips/select.ll

Differential Revision: https://reviews.llvm.org/D35408

llvm-svn: 308595

Fixes PR33841.

llvm-svn: 308591

We should use SHLX and similar instructions for these patterns, but we currently don't.

llvm-svn: 308590

I've stripped the checks for 64-bit types in 32-bit mode to match the existing tests.

llvm-svn: 308589

The test issue was fixed and the test was updated in r244577, but the comment wasn't removed.

llvm-svn: 308588

Add optimization remarks support to the PrologueEpilogueInserter. For
now, emit the stack size as an analysis remark, but more additions wrt
shrink-wrapping may be added.

https://reviews.llvm.org/D35645

llvm-svn: 308556

The first argument needs to be an immediate rather than a register. Should fix
some crashes in the verifier bot.

llvm-svn: 308540

llvm-svn: 308527

and non-debug units.

Patch by Andrea DiBiagio.

Differential Revision:  https://reviews.llvm.org/D35637

llvm-svn: 308513

llvm-svn: 308510

Fixes the crash reported in PR33844.

llvm-svn: 308503

llvm-svn: 308493