Commits · 790878f291fa5dc58a1c560cb6cc76fd1bfd1c5a · Roger Ferrer / llvm-epi · GitLab

Aug 17, 2020
- AMDGPU/GlobalISel: Match global saddr addressing mode · a9ee0589
  Matt Arsenault authored Aug 16, 2020
  
  a9ee0589
- AMDGPU: Match global saddr addressing mode · e1a2f471
  Matt Arsenault authored Aug 13, 2020
  e1a2f471
- [AMDGPU] Define spill opcodes for all AGPR sizes · 24182f14
  Stanislav Mekhanoshin authored Aug 17, 2020
  24182f14
- AMDGPU/GlobalISel: Look through copies in getPtrBaseWithConstantOffset · c8a98722
  Matt Arsenault authored Aug 15, 2020
  c8a98722
- Reset PAL metadata when AMDGPU traget stream finishes · eed6476a
  Steven Perron authored Aug 17, 2020
  eed6476a
- AMDGPU/GlobalISel: Fix missing 256-bit AGPR mapping · c7b9cd31
  Matt Arsenault authored Aug 12, 2020
  
  c7b9cd31
- AMDGPU/GlobalISel: Fix using readfirstlane with ballot intrinsics · af162ac7
  Matt Arsenault authored Aug 12, 2020
  af162ac7
- AMDGPU: Don't look at dbg users for foldable operands · da3f357d
  Matt Arsenault authored Jul 22, 2020
  da3f357d
- AMDGPU/GlobalISel: Fix using post-legal combiner without LegalizerInfo · 66ffa0e9
  Matt Arsenault authored Aug 15, 2020
  
  66ffa0e9
- AMDGPU: Fix using wrong offsets for global atomic fadd intrinsics · e0375dbc
  Matt Arsenault authored Aug 14, 2020
  e0375dbc
- [RISCV] Enable the use of the old mucounteren name · 3f7068ad
  Sam Elliott authored Aug 17, 2020
  3f7068ad
- [RISCV] Indirect branch generation in position independent code · 5f9ecc5d
  Sam Elliott authored Aug 17, 2020
  5f9ecc5d
- [X86][AVX] Move lowerShuffleWithVPMOV inside explicit shuffle lowering cases · 1d2ede87
  Simon Pilgrim authored Aug 17, 2020
  1d2ede87
- [VE] Support f128 · 40f1e7e8
  Kazushi (Jam) Marukawa authored Jun 27, 2020
  40f1e7e8
- [X86] Reject dirflag in inline asm constraints other than clobber. · a206f850
  Craig Topper authored Aug 16, 2020
  a206f850
- [PowerPC] Make StartMI ignore COPY like instructions. · 4d52ebb9
  Chen Zheng authored Aug 10, 2020
  4d52ebb9
Aug 16, 2020
- [X86][AVX] Fold CONCAT(HOP(X,Y),HOP(Z,W)) -> HOP(CONCAT(X,Z),CONCAT(Y,W)) for float types · f25d47b7
  Simon Pilgrim authored Aug 16, 2020
  f25d47b7
- [X86][SSE] Replace combineShuffleWithHorizOp with canonicalizeShuffleMaskWithHorizOp · dca7eb7d
  Simon Pilgrim authored Aug 16, 2020
  dca7eb7d
- [X86] isRepeatedTargetShuffleMask - don't require specific MVT type. NFC. · c27baa54
  Simon Pilgrim authored Aug 16, 2020
  c27baa54
Aug 15, 2020
- [GlobalISel] Enable copy-propagation in post-legalizer combiner. · 7006bb69
  Amara Emerson authored Aug 14, 2020
  7006bb69
- AMDGPU: Remove register class params from flat memory patterns · f0af434b
  Matt Arsenault authored Aug 14, 2020
  
  f0af434b
- AMDGPU: Fix global atomic saddr operand class · a7455652
  Matt Arsenault authored Aug 14, 2020
  
  a7455652
- AMDGPU: Remove slc from flat offset complex patterns · 625db2fe
  Matt Arsenault authored Aug 14, 2020
  625db2fe
- AMDGPU: Fix matching wrong offsets for global atomic loads · e5077b5c
  Matt Arsenault authored Aug 13, 2020
  e5077b5c
- AMDGPU: Remove redundant FLAT complex patterns · 8cb02298
  Matt Arsenault authored Aug 13, 2020
  8cb02298
- AMDGPU: Correct definitions for global saddr instructions · 47af1ac6
  Matt Arsenault authored Aug 11, 2020
  47af1ac6
- AMDGPU: Remove SIFixupVectorISel pass · 79298a50
  Matt Arsenault authored Aug 13, 2020
  79298a50
- [AMDGPU] Fix MAI ld/st hazard handling · 43a38dc2
  Stanislav Mekhanoshin authored Aug 14, 2020
  43a38dc2
- [SVE] Lower fixed length vXi32/vXi64 SDIV to scalable vectors. · 92593f9e
  Cameron McInally authored Aug 14, 2020
  92593f9e
- Fix TargetSubtargetInfo derivatives after D85165 · 58f5966d
  Fangrui Song authored Aug 14, 2020
  
  58f5966d
- [X86][MC][Target] Initial backend support a tune CPU to support -mtune · c7a0b268
  Craig Topper authored Aug 14, 2020
  c7a0b268
Aug 14, 2020
- [AIX] Generate unique module id based on Pid and timestamp · f759b4e4
  Xiangling Liao authored Aug 07, 2020
  f759b4e4
- [X86][SSE] Fold HOP(SHUFFLE(X),SHUFFLE(Y)) --> SHUFFLE(HOP(X,Y)) · e9eb2dc3
  Simon Pilgrim authored Aug 14, 2020
  e9eb2dc3
- AMDGPU/GlobalISel: Match andn2/orn2 for more types · 40a142fa
  Matt Arsenault authored Jul 31, 2020
  40a142fa
- [VE] Remove obsolete I8/I16 register classes · 2f01af76
  Kazushi (Jam) Marukawa authored Aug 13, 2020
  2f01af76
- [NFC][ARM] Port MaybeCall into ARMTTImpl method · eb82d58f
  Sam Parker authored Aug 14, 2020
  eb82d58f
- [AMDGPU] Enable .rodata for amdpal os · 9aa0ff77
  Sebastian Neubauer authored Aug 13, 2020
  9aa0ff77
- [SVE] Fix bug in SVEIntrinsicOpts::optimizePTest · 6c7957c9
  David Sherwood authored Aug 13, 2020
  6c7957c9
Aug 13, 2020
- Revert "[ARM] Fix IT block generation after Thumb2SizeReduce with -Oz" · 0c390c22
  David Green authored Aug 13, 2020
  0c390c22
- [AMDGPU] Fix FP/BP spills when MUBUF constant offset exceeded · 7d1cb187
  Austin Kerbow authored Aug 11, 2020
  7d1cb187