Commits · 8b00b24f8505970f54eab85aad8db5845a635850 · Roger Ferrer / llvm-epi · GitLab

Sep 27, 2022
- [VP][RISCV] Add vp.ceil and RISC-V support · 8b00b24f
  eopXD authored Sep 24, 2022
  8b00b24f
- [Hexagon] Unify getSizeOfs in HexagonVectorCombine, NFC · 7da2b918
  Krzysztof Parzyszek authored Sep 27, 2022
  
  7da2b918
- [Hexagon] Move function to a different class, NFC · 9c9e877b
  Krzysztof Parzyszek authored Sep 27, 2022
  9c9e877b
- [ObjC][ARC] Fix target register for call expanded from CALL_RVMARKER on Windows · ed8409df
  Stefan Gränitz authored Sep 27, 2022
  ed8409df
- [AArch64] Remove incorrect zero element insert-bitcast patterns · 401481da
  David Green authored Sep 27, 2022
  401481da
- [RISCV] Rename getVectorImmCost to getStoreImmCost [nfc] · 77b202f9
  Philip Reames authored Sep 27, 2022
  77b202f9
- [LoongArch] Add some comments for expand pseudo-inst pass. NFC · 823ce6ad
  wanglei authored Sep 27, 2022
  823ce6ad
- [VE] Change to expand FPOW · de801320
  Kazushi (Jam) Marukawa authored Sep 27, 2022
  de801320
- [LoongArch] Support lowering frames larger than 2048 bytes · c2a44b59
  WANG Xuerui authored Sep 27, 2022
  c2a44b59
- [AArch64] Add Neoverse V2 CPU support · fbb11941
  David Sherwood authored Sep 15, 2022
  fbb11941
- [WebAssembly] Use intrinsics for table.get/set instructions · 1bd1a440
  Paulo Matos authored Sep 27, 2022
  1bd1a440
- [VP][RISCV] Add vp.maxnum and vp.minnum intrinsics and RISC-V support. · 04e1301f
  Yeting Kuo authored Sep 26, 2022
  04e1301f
- Revert "[AMDGPU] Move SIModeRegisterDefaults to SI MFI" · 20a80d60
  Vitaly Buka authored Sep 26, 2022
  20a80d60
- [PowerPC] XCOFF exception section support on the direct assembler path · ce004fb4
  Paul Scoropan authored Sep 26, 2022
  ce004fb4
Sep 26, 2022
- [AMDGPU] Move SIModeRegisterDefaults to SI MFI · 0ce96e06
  Stanislav Mekhanoshin authored Sep 26, 2022
  0ce96e06
- [Hexagon] Avoid some unnecessary sign-extend instructions · dfaf7a28
  Krzysztof Parzyszek authored Sep 26, 2022
  dfaf7a28
- [Hexagon] Make sure we can still shift scalar vectors by non-splats · d6c0a5be
  Krzysztof Parzyszek authored Sep 26, 2022
  
  d6c0a5be
- AMDGPU: Handle new address pattern in LowerKernelAttributes introduced by opaque pointers · dee4bc4a
  Changpeng Fang authored Sep 26, 2022
  dee4bc4a
- [VE] Disable automatic maxnum/minnum selection · 1cef30b9
  Kazushi (Jam) Marukawa authored Sep 25, 2022
  1cef30b9
- [VE] Support smax/smin · 76c76e9a
  Kazushi (Jam) Marukawa authored Sep 24, 2022
  76c76e9a
- [ARM] Enable and/cmp0 folding · 66021101
  Momchil Velikov authored Sep 26, 2022
  66021101
- [AArch64] Enable FeatureFuseAdrpAdd for all Arm cpus · bebc9695
  David Green authored Sep 26, 2022
  bebc9695
- [LoongArch] Add codegen support for strict_fsetccs and any_fsetcc · a6d699b5
  gonglingqin authored Sep 26, 2022
  a6d699b5
- [LoongArch] Lower BlockAddress/JumpTable · 75265c7f
  wanglei authored Sep 26, 2022
  75265c7f
- [VP][RISCV] Add vp.sqrt intrinsic and RISC-V support. · 43c5fbdd
  Yeting Kuo authored Sep 12, 2022
  43c5fbdd
- [LoongArch] Support 'generic' as a valid CPU name · ad6fe320
  WANG Xuerui authored Sep 26, 2022
  ad6fe320
- Add override for runOnFunction() · bf25a489
  Ruiling Song authored Sep 26, 2022
  bf25a489
- [LoongArch] Support fastcc and treat it as ccc · d2ac89b6
  WANG Xuerui authored Sep 26, 2022
  d2ac89b6
- [LoongArch] Support llvm.thread.pointer · f89f0990
  WANG Xuerui authored Sep 26, 2022
  f89f0990
- AMDGPU: Add a pass to rewrite certain undef in PHI · cf14c7ca
  Ruiling Song authored Sep 13, 2022
  cf14c7ca
- [Clang][LoongArch] Add inline asm support for constraints f/l/I/K · 394f3091
  Weining Lu authored Sep 22, 2022
  394f3091
Sep 25, 2022
- [AVR] Fix useDeprecatedPositionallyEncodedOperands errors. · 4f188ef8
  James Y Knight authored Sep 19, 2022
  4f188ef8
- [AMDGPU] Fix useDeprecatedPositionallyEncodedOperands errors in R600. · a8c59bcc
  James Y Knight authored Sep 16, 2022
  a8c59bcc
- [Lanai] Fix useDeprecatedPositionallyEncodedOperands errors. · 0f99958e
  James Y Knight authored Jun 12, 2022
  0f99958e
- [CostModel][X86] Add missing cost kinds for v2i64 icmp on SLM · 196f27bb
  Simon Pilgrim authored Sep 25, 2022
  
  196f27bb
- [X86] Fix Icelake VPMULLQ zmm pipes and adjust AVX512DQ v8i64 mul costs to match worse case · faff990e
  Simon Pilgrim authored Sep 25, 2022
  faff990e
- [AMDGPU] Pattern for flat atomic fadd f64 intrinsic with local addr · dcc756d0
  Petar Avramovic authored Sep 25, 2022
  dcc756d0
- [RISCV] Pattern match scalable strided load/store · 5358968e
  Philip Reames authored Sep 24, 2022
  5358968e
- [RISCV] Add lowering for scalable @llvm.riscv.masked.strided.load/store · 6e7c54ec
  Philip Reames authored Sep 24, 2022
  6e7c54ec
Sep 24, 2022
- [TableGen] Add useDeprecatedPositionallyEncodedOperands option. · 5351878b
  James Y Knight authored Sep 20, 2022
  5351878b