[AMDGPU] Constrain the AMDGPU inliner on maximum number of basic blocks in a caller function (compile time performance)

Differential revision: https://reviews.llvm.org/D62917

llvm-svn: 362789

It was added by D46654 but is actually never used.
R_PPC64_CALL_PLT (was: R_PPC_CALL_PLT) is a static link-time constant.

Reviewed By: ruiu

Differential Revision: https://reviews.llvm.org/D62994

llvm-svn: 362788

These builtins should work with immediate or variable shift operand for
gcc compatibility.

Differential Revision: https://reviews.llvm.org/D62850

llvm-svn: 362786

Summary:
- when a method is not available because of the target value kind (e.g. an &&
  method on a Foo& variable), then don't offer it.
- when a method is effectively shadowed by another method from the same class
  with a) an identical argument list and b) superior qualifiers, then don't
  offer it.

Reviewers: ilya-biryukov

Subscribers: cfe-commits

Tags: #clang

Differential Revision: https://reviews.llvm.org/D62582

llvm-svn: 362785

llvm-svn: 362784

Summary:
The DWARFCompileUnit is set as the "user data" of the lldb compile unit
directly in the constructor (see ParseCompileUnit).

This means that instead of going through unit indexes, we can just fetch
the DWARF unit directly from there.

Reviewers: clayborg, JDevlieghere

Subscribers: aprantl, jdoerfert, lldb-commits

Differential Revision: https://reviews.llvm.org/D62943

llvm-svn: 362783

I replaced the circular library dependency with a forward declaration,
but it is only a workaround, not a real fix.

llvm-svn: 362782

Support intel -march=cooperlake in clang

Patch by Shengchen Kan (skan)

Differential Revision: https://reviews.llvm.org/D62835

llvm-svn: 362781

Summary:
This patch fixes a bug in the assembler that permitted a type suffix on
predicate registers when not expected. For instance, the following was
previously valid:

    faddv h0, p0.q, z1.h

This bug was present in all SVE instructions containing predicates with
no type suffix and no predication form qualifier, i.e. /z or /m. The
latter instructions are already caught with an appropiate error message
by the assembler, e.g.:

            .text
    <stdin>:1:13: error: not expecting size suffix
    cmpne p1.s, p0.b/z, z2.s, 0
                ^

A similar issue for SVE vector registers was fixed in:

  https://reviews.llvm.org/D59636

Reviewed By: SjoerdMeijer

Differential Revision: https://reviews.llvm.org/D62942

llvm-svn: 362780

Patch by Sander de Smalen (sdesmalen)

Reviewed By: SjoerdMeijer

Differential Revision: https://reviews.llvm.org/D62941

llvm-svn: 362779

This is https://bugs.llvm.org/show_bug.cgi?id=42122.

If an object file has a size less than program header's file [offset + size]
(i.e. if we have overflow), llvm-objcopy crashes instead of reporting a
error.

The patch fixes this issue.

Differential revision: https://reviews.llvm.org/D62898

llvm-svn: 362778

This is a refactoring follow-up for D62809
"Change how we handle implicit sections.".
It allows to simplify the code.

Differential revision: https://reviews.llvm.org/D62912

llvm-svn: 362777

Support intel -march=cooperlake in llvm

Patch by Shengchen Kan (skan)

Differential Revision: https://reviews.llvm.org/D62836

llvm-svn: 362776

Removed unused (in non-debug builds) variable.

llvm-svn: 362775

    
Patch which introduces a target-independent framework for generating
hardware loops at the IR level. Most of the code has been taken from
PowerPC CTRLoops and PowerPC has been ported over to use this generic
pass. The target dependent parts have been moved into
TargetTransformInfo, via isHardwareLoopProfitable, with
HardwareLoopInfo introduced to transfer information from the backend.
    
Three generic intrinsics have been introduced:
- void @llvm.set_loop_iterations
  Takes as a single operand, the number of iterations to be executed.
- i1 @llvm.loop_decrement(anyint)
  Takes the maximum number of elements processed in an iteration of
  the loop body and subtracts this from the total count. Returns
  false when the loop should exit.
- anyint @llvm.loop_decrement_reg(anyint, anyint)
  Takes the number of elements remaining to be processed as well as
  the maximum numbe of elements processed in an iteration of the loop
  body. Returns the updated number of elements remaining.

llvm-svn: 362774

In r356860, the legalization logic for BSWAP was modified to ISD::ROTL,
rather than the old ISD::{SHL, SRL, OR} nodes.

This works fine on AVR for 8-bit rotations, but 16-bit rotations are
currently unimplemented - they always trigger an assertion error in the
AVRExpandPseudoInsts pass ("RORW unimplemented").

This patch instructions the legalizer to expand 16-bit rotations into
the previous SHL, SRL, OR pattern it did previously.

This fixes the 'issue-cannot-select-bswap.ll' test. Interestingly, this
test failure seems flaky - it passes successfully on the avr-build-01
buildbot, but fails locally on my Arch Linux install.

llvm-svn: 362773

llvm-svn: 362772

[llvm-objdump] Print source when subsequent lines in the translation unit come from the same line in two different headers.

Reviewers: grimar, rupprecht, jhenderson

Reviewed By: grimar, jhenderson

Subscribers: llvm-commits, jhenderson

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D62461

llvm-svn: 362771

Differential Revision: https://reviews.llvm.org/D62933

llvm-svn: 362770

When a function is excluded via comdat we shouldn't add it to the
final list of init functions.

Differential Revision: https://reviews.llvm.org/D62983

llvm-svn: 362769

Summary: Fixes Bug 41904 https://bugs.llvm.org/show_bug.cgi?id=41904

Reviewers: jhenderson, rupprecht, grimar, MaskRay

Reviewed By: jhenderson, rupprecht, MaskRay

Subscribers: dexonsmith, rupprecht, kristina, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D62275

llvm-svn: 362768

We should keep the symbol type (STT_GNU_IFUNC) for a local ifunc because
it may result in an IRELATIVE reloc that the dynamic loader will use to
resolve the address at startup time.

There is another problem that is not fixed by this patch: a PC relative
relocation should also create a relocation with the ifunc symbol.

llvm-svn: 362767

Subscribers: mgorny, mgrang, dexonsmith, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D62992

llvm-svn: 362766

The android_compile.py script requires one.

llvm-svn: 362764

llvm-svn: 362763

llvm-svn: 362762

llvm-svn: 362761

This already forced a skip for VMEM, so it should also be done for
flat. I'm somewhat skeptical about the benefit of this though.

llvm-svn: 362760

Use the PPC vector min/max instructions for computing the corresponding
operation as these should be faster than the compare/select sequences
we currently emit.

Differential revision: https://reviews.llvm.org/D47332

llvm-svn: 362759

to try and fix android buildbot. Also make sure that the empty dummy
test contains an output file name so the android_build.py wrapper script
doesn't check fail.

llvm-svn: 362758

referenced.

This reinstates r362563, reverted in r362597.

llvm-svn: 362757

most / all other Expr subclasses.

This reinstates r362551, reverted in r362597, with a fix to a bug that
caused MemberExprs to sometimes have a null FoundDecl after a round-trip
through an AST file.

llvm-svn: 362756

This reverts r362355 (git commit c78c999a)

This causes some internal tests to fail; details provided offthread.

llvm-svn: 362755

SIInsertSkips really doesn't understand the control flow, and makes
very stupid assumptions about the block layout. This was able to get
away with not skipping return blocks, since usually after
structurization there is only one placed at the end of the
function. Tail duplication can break this assumption.

llvm-svn: 362754

As per the Developer Policy, upon obtaining commit access.

llvm-svn: 362753

llvm-svn: 362752

Incorrect Debug Variable Range was calculated while "COMPUTING LIVE DEBUG VARIABLES" stage.
Range for Debug Variable("i") computed according to current state of instructions
inside of basic block. But Register Allocator creates new instructions which were not taken
into account when Live Debug Variables computed. In the result DBG_VALUE instruction for
the "i" variable was put after these newly inserted instructions. This is incorrect.
Debug Value for the loop counter should be inserted before any loop instruction.

Differential Revision: https://reviews.llvm.org/D62650

llvm-svn: 362750

   "Divergence driven ISel. Assign register class for cross block values
       according to the divergence."
       that discovered the design flaw leading to several issues that
       required to be solved before.

       This change reverts AMDGPU specific changes and keeps common part
       unaffected.

llvm-svn: 362749

llvm-svn: 362748

This primarily affects add/fadd/mul/fmul/and/or/xor/pmuludq/pmuldq/max/min/fmaxc/fminc/pmaddwd/pavg.

We already commuted the unmasked and zero masked versions.

I've added 512-bit stack folding tests for most of the instructions
affected. I've tested needing commuting and not commuting across
unmasked, merged masked, and zero masked. The 128/256 bit instructions
should behave similarly.

llvm-svn: 362746